verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc_def09.v" 1
verilog/inc_def09.v:1: COMMENT: // DESCRIPTION: Verilog-Perl: Verilog Test module
verilog/inc_def09.v:1:  /*CMT*/  
verilog/inc_def09.v:2: COMMENT: //
verilog/inc_def09.v:2:  /*CMT*/  
verilog/inc_def09.v:3: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc_def09.v:3:  /*CMT*/  
verilog/inc_def09.v:4: COMMENT: // without warranty, 2009 by Wilson Snyder.
verilog/inc_def09.v:4:  /*CMT*/  
verilog/inc_def09.v:5: 
verilog/inc_def09.v:6: 
verilog/inc_def09.v:7: 
verilog/inc_def09.v:8: COMMENT: // Definitions as speced
verilog/inc_def09.v:8:  /*CMT*/  
verilog/inc_def09.v:9: COMMENT: // Note there are trailing spaces, which spec doesn't show properly
verilog/inc_def09.v:9:  /*CMT*/  
verilog/inc_def09.v:10:  
verilog/inc_def09.v:11: 'DS<initial $display("start", "msg1" , "msg2", "end");>'
verilog/inc_def09.v:12: 'initial $display("start", "msg1"  , "msg2" , "end");'
verilog/inc_def09.v:13: 'DS<initial $display("start", " msg1" , , "end");>'
verilog/inc_def09.v:14: 'initial $display("start", " msg1" , , "end");'
verilog/inc_def09.v:15: 'DS<initial $display("start",  , "msg2 ", "end");>'
verilog/inc_def09.v:16: 'initial $display("start",  , "msg2 ", "end");'
verilog/inc_def09.v:17: 'DS<initial $display("start",  , , "end");>'
verilog/inc_def09.v:18: 'initial $display("start",  , , "end");'
verilog/inc_def09.v:19: 'DS<initial $display("start",  , , "end");>'
verilog/inc_def09.v:20: 'initial $display("start",  , , "end");'
verilog/inc_def09.v:21: COMMENT: //`D("msg1") // ILLEGAL: only one argument
verilog/inc_def09.v:21:  /*CMT*/  
verilog/inc_def09.v:22: COMMENT: //`D()       // ILLEGAL: only one empty argument
verilog/inc_def09.v:22:  /*CMT*/  
verilog/inc_def09.v:23: COMMENT: //`D(,,)     // ILLEGAL: more actual than formal arguments
verilog/inc_def09.v:23:  /*CMT*/  
verilog/inc_def09.v:24: 
verilog/inc_def09.v:25: COMMENT: // Defaults:
verilog/inc_def09.v:25:  /*CMT*/  
verilog/inc_def09.v:26:  
verilog/inc_def09.v:27: 'DS<$display(5,,2,,3);>'
verilog/inc_def09.v:28: '$display(5,,2,,3);'
verilog/inc_def09.v:29: 'DS<$display(1,,"B",,3);>'
verilog/inc_def09.v:30: '$display(1 ,,"B",,3 );'
verilog/inc_def09.v:31: 'DS<$display(5,,2,,);>'
verilog/inc_def09.v:32: '$display(5,,2,,);'
verilog/inc_def09.v:33: COMMENT: //`MACRO1 ( 1 )  // ILLEGAL: b and c omitted, no default for c
verilog/inc_def09.v:33:  /*CMT*/  
verilog/inc_def09.v:34: 
verilog/inc_def09.v:35:  
verilog/inc_def09.v:36: 'DS<$display(1,,,,3);>'
verilog/inc_def09.v:37: '$display(5,,,,"C");'
verilog/inc_def09.v:38: 'DS<$display(5,,2,,"C");>'
verilog/inc_def09.v:39: '$display(5,,2,,"C");'
verilog/inc_def09.v:40: 'DS<$display(5,,2,,"C");>'
verilog/inc_def09.v:41: '$display(5,,2,,"C");'
verilog/inc_def09.v:42: 
verilog/inc_def09.v:43:  
verilog/inc_def09.v:44: 'DS<$display(1,,0,,"C");>'
verilog/inc_def09.v:45: '$display(1 ,,0,,"C");'
verilog/inc_def09.v:46: 'DS<$display(5,,0,,"C");>'
verilog/inc_def09.v:47: '$display(5,,0,,"C");'
verilog/inc_def09.v:48: COMMENT: //`MACRO3    // ILLEGAL: parentheses required
verilog/inc_def09.v:48:  /*CMT*/  
verilog/inc_def09.v:49: 
verilog/inc_def09.v:50:  
verilog/inc_def09.v:51: 'DS<DS<b + 1> + DS<42 + a>>'
verilog/inc_def09.v:52: 'b + 1 + 42 + a'
verilog/inc_def09.v:53: 
verilog/inc_def09.v:54: COMMENT: // Local tests
verilog/inc_def09.v:54:  /*CMT*/  
verilog/inc_def09.v:55:  
verilog/inc_def09.v:56: DS<'"==)" "((((" () '>;
verilog/inc_def09.v:57: '"==)" "((((" () ';
verilog/inc_def09.v:58: 
verilog/inc_def09.v:59: COMMENT: // Also check our line counting doesn't go bad
verilog/inc_def09.v:59:  /*CMT*/  
verilog/inc_def09.v:62:  
verilog/inc_def09.v:62: 
verilog/inc_def09.v:62: 
verilog/inc_def09.v:63: 
verilog/inc_def09.v:64: 
verilog/inc_def09.v:65: 
verilog/inc_def09.v:66: 
verilog/inc_def09.v:67: 
verilog/inc_def09.v:68: 
verilog/inc_def09.v:69: 
verilog/inc_def09.v:70: DS<'(6) (eq=al) ZOT'>
verilog/inc_def09.v:71: HERE-71 - Line71
verilog/inc_def09.v:72: 
verilog/inc_def09.v:73: COMMENT: //======================================================================
verilog/inc_def09.v:73:  /*CMT*/  
verilog/inc_def09.v:74: 
verilog/inc_def09.v:75: `line 75 "verilog/inc_def09.v" 2
verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0
verilog/inc_nonl.v:1: COMMENT: // The lack of a newline on the next line is intentional
verilog/inc_nonl.v:1:  /*CMT*/  
verilog/inc_nonl.v:2: blah-no-newline-here>
verilog/inc_nonl.v:3: `line 3 "verilog/inc_nonl.v" 2
verilog/inc_ifdef.v:1: `line 1 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc_ifdef.v:1:  /*CMT*/  
verilog/inc_ifdef.v:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc_ifdef.v:2:  /*CMT*/  
verilog/inc_ifdef.v:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/inc_ifdef.v:3:  /*CMT*/  
verilog/inc_ifdef.v:4: 
verilog/inc_ifdef.v:5:  
verilog/inc_ifdef.v:6:  
verilog/inc_ifdef.v:7:    
verilog/inc_ifdef.v:8: 
verilog/inc_ifdef.v:9: 
verilog/inc_ifdef.v:10:  
verilog/inc_ifdef.v:11:  
verilog/inc_ifdef.v:12:   $display("1A");
verilog/inc_ifdef.v:13:   
verilog/inc_ifdef.v:14:   
verilog/inc_ifdef.v:15:   
verilog/inc_ifdef.v:16:   $display("2A");
verilog/inc_ifdef.v:17:    
verilog/inc_ifdef.v:18:   
verilog/inc_ifdef.v:19:    
verilog/inc_ifdef.v:20:   
verilog/inc_ifdef.v:21:   
verilog/inc_ifdef.v:22:   $display("3AELSE");
verilog/inc_ifdef.v:23:   
verilog/inc_ifdef.v:24:  
verilog/inc_ifdef.v:25:   
verilog/inc_ifdef.v:26:  
verilog/inc_ifdef.v:27:  
verilog/inc_ifdef.v:28:   
verilog/inc_ifdef.v:29:    
verilog/inc_ifdef.v:30:   
verilog/inc_ifdef.v:31:    
verilog/inc_ifdef.v:32:   
verilog/inc_ifdef.v:33:   
verilog/inc_ifdef.v:34:   
verilog/inc_ifdef.v:35:   
verilog/inc_ifdef.v:36:  
verilog/inc_ifdef.v:37:   
verilog/inc_ifdef.v:38: 
verilog/inc_ifdef.v:39:   
verilog/inc_ifdef.v:40: 
verilog/inc_ifdef.v:41: 
verilog/inc_ifdef.v:42: `line 42 "verilog/inc_ifdef.v" 2
verilog/inc2.v:1: `line 1 "verilog/inc2.v" 0
verilog/inc2.v:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc2.v:1:  /*CMT*/  
verilog/inc2.v:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc2.v:2:  /*CMT*/  
verilog/inc2.v:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/inc2.v:3:  /*CMT*/  
verilog/inc2.v:4: At file "verilog/inc2.v"  line 4
verilog/inc2.v:5:  
verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0
verilog/inc2.v:5: `line 1 "verilog/t_preproc_inc3.vh" 1
verilog/t_preproc_inc3.vh:1: `line 2 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:2: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
inc3_a_filename_from_line_directive:2:  /*CMT*/  
inc3_a_filename_from_line_directive:3: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
inc3_a_filename_from_line_directive:3:  /*CMT*/  
inc3_a_filename_from_line_directive:4: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
inc3_a_filename_from_line_directive:4:  /*CMT*/  
inc3_a_filename_from_line_directive:5: 
inc3_a_filename_from_line_directive:6:  
inc3_a_filename_from_line_directive:7:   
inc3_a_filename_from_line_directive:8:   
inc3_a_filename_from_line_directive:9: COMMENT: // FOO
inc3_a_filename_from_line_directive:9:    /*CMT*/  
inc3_a_filename_from_line_directive:10:   At file "inc3_a_filename_from_line_directive"  line 10
inc3_a_filename_from_line_directive:11: 
inc3_a_filename_from_line_directive:12:    
inc3_a_filename_from_line_directive:13: COMMENT: // guard
inc3_a_filename_from_line_directive:13:   /*CMT*/  
inc3_a_filename_from_line_directive:14: 
inc3_a_filename_from_line_directive:15:  
inc3_a_filename_from_line_directive:16:   
inc3_a_filename_from_line_directive:17: 
inc3_a_filename_from_line_directive:18: 
inc3_a_filename_from_line_directive:19: `line 19 "inc3_a_filename_from_line_directive" 2
verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0
verilog/inc2.v:5: 
verilog/inc2.v:6:   
verilog/inc2.v:7: `line 7 "verilog/inc2.v" 2
verilog/inc1.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc1.v:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc1.v:1:  /*CMT*/  
verilog/inc1.v:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc1.v:2:  /*CMT*/  
verilog/inc1.v:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/inc1.v:3:  /*CMT*/  
verilog/inc1.v:4:    text.
verilog/inc1.v:5: 
verilog/inc1.v:6: COMMENT: //===========================================================================
verilog/inc1.v:6:  /*CMT*/  
verilog/inc1.v:7: COMMENT: // Includes
verilog/inc1.v:7:  /*CMT*/  
verilog/inc1.v:8: 
verilog/inc1.v:9: COMMENT: //===========================================================================
verilog/inc1.v:9:  /*CMT*/  
verilog/inc1.v:10: COMMENT: // Defines
verilog/inc1.v:10:  /*CMT*/  
verilog/inc1.v:11: 
verilog/inc1.v:12:  
verilog/inc1.v:13:  
verilog/inc1.v:14: COMMENT: // DEF_A0 set by command line
verilog/inc1.v:14:  /*CMT*/  
verilog/inc1.v:15:    wire [3:0] q = {
verilog/inc1.v:16: 		     1'b1    ,
verilog/inc1.v:17: 		       1'b0  ,
verilog/inc1.v:18: 		     1'b1    ,
verilog/inc1.v:19: 		       1'b0 
verilog/inc1.v:20: 		   };
verilog/inc1.v:21: 
verilog/inc1.v:22: text.
verilog/inc1.v:23: 
verilog/inc1.v:24:  
verilog/inc1.v:25: COMMENT: // but not
verilog/inc1.v:25:  
verilog/inc1.v:26: COMMENT: /*this */
verilog/inc1.v:26: COMMENT: /* this too */
verilog/inc1.v:26: DS<foo  /*CMT*/   bar    /*CMT*/  >
verilog/inc1.v:27: COMMENT: /*CMT*/
verilog/inc1.v:27: DS<foobar2   /*CMT*/  >
verilog/inc1.v:28: 
verilog/inc1.v:29:  
verilog/inc1.v:29: 
verilog/inc1.v:29: 
verilog/inc1.v:32: 
verilog/inc1.v:33:  
verilog/inc1.v:33: 
verilog/inc1.v:33: 
verilog/inc1.v:33: 
verilog/inc1.v:37: 
verilog/inc1.v:38: COMMENT: /*******COMMENT*****/
verilog/inc1.v:38:  /*CMT*/  
verilog/inc1.v:39: DS<first part 
verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0
verilog/inc1.v:39:   		second part 
verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0
verilog/inc1.v:39:   		third part>
verilog/inc1.v:40: DS<{
verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0
verilog/inc1.v:40: 		       a,
verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0
verilog/inc1.v:40: 		       b,
verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0
verilog/inc1.v:40: 		       c}>
verilog/inc1.v:41: Line_Preproc_Check 41
verilog/inc1.v:42: 
verilog/inc1.v:43: COMMENT: //===========================================================================
verilog/inc1.v:43:  /*CMT*/  
verilog/inc1.v:44: 
verilog/inc1.v:45:  
verilog/inc1.v:46: 
verilog/inc1.v:47:  
verilog/inc1.v:48:  
verilog/inc1.v:49: DS<DS<deep> DS<deep>>
verilog/inc1.v:50: 
verilog/inc1.v:51:  
verilog/inc1.v:52:  
verilog/inc1.v:53: "Inside: `nosubst"
verilog/inc1.v:54: "`nosubst"
verilog/inc1.v:55: 
verilog/inc1.v:56:  
verilog/inc1.v:57: DS<x y LLZZ x y>
verilog/inc1.v:58: DS<DS<p q LLZZ p q> DS<r s LLZZ r s> LLZZ DS<p q LLZZ p q> DS<r s LLZZ r s>>
verilog/inc1.v:59: 
verilog/inc1.v:60: 
verilog/inc1.v:61: 
verilog/inc1.v:62: DS<firstline comma","line LLZZ firstline comma","line>
verilog/inc1.v:63: 
verilog/inc1.v:64:  
verilog/inc1.v:65: COMMENT: // Simulators disagree here; some substitute "a" others do not
verilog/inc1.v:65: DS<x y LLZZ "x" y>   /*CMT*/  
verilog/inc1.v:66: 
verilog/inc1.v:67:  
verilog/inc1.v:68: DS<(a,b)>(a,b)
verilog/inc1.v:69: 
verilog/inc1.v:70:  
verilog/inc1.v:71: $display(DS<"left side: \"right side\"">)
verilog/inc1.v:72: 
verilog/inc1.v:73:  
verilog/inc1.v:74: DS<bar_suffix>  more
verilog/inc1.v:75: 
verilog/inc1.v:76:  
verilog/inc1.v:76: 
verilog/inc1.v:78: DS<
verilog/inc1.v:78: `line 78 "verilog/inc1.v" 0
verilog/inc1.v:78: 	$c("Zap(\"",bug1,"\");");>;
verilog/inc1.v:79: DS<
verilog/inc1.v:79: `line 79 "verilog/inc1.v" 0
verilog/inc1.v:79: 	$c("Zap(\"","bug2","\");");>;
verilog/inc1.v:80: 
verilog/inc1.v:81: COMMENT: /* Define inside comment: `DEEPER and `WITHTICK */
verilog/inc1.v:81:  /*CMT*/  
verilog/inc1.v:82: COMMENT: // More commentary: `zap(bug1); `zap("bug2");
verilog/inc1.v:82:  /*CMT*/  
verilog/inc1.v:83: 
verilog/inc1.v:84: COMMENT: //======================================================================
verilog/inc1.v:84:  /*CMT*/  
verilog/inc1.v:85: COMMENT: // display passthru
verilog/inc1.v:85:  /*CMT*/  
verilog/inc1.v:86: 
verilog/inc1.v:87:  
verilog/inc1.v:88:  
verilog/inc1.v:89:  
verilog/inc1.v:90:  
verilog/inc1.v:91: COMMENT: // Doesn't expand
verilog/inc1.v:91:  
verilog/inc1.v:92:  
verilog/inc1.v:93:    initial begin
verilog/inc1.v:94: COMMENT: //$display(`msg( \`, \`));  // Illegal
verilog/inc1.v:94:        /*CMT*/  
verilog/inc1.v:95:       $display(DS<"pre DS<thrupre DS<thrumid> thrupost> post: \"right side\"">);
verilog/inc1.v:96:       $display(DS<"left side: \"right side\"">);
verilog/inc1.v:97:       $display(DS<"left side: \"right side\"">);
verilog/inc1.v:98:       $display(DS<"DS<left_side>: \"DS<right_side>\"">);
verilog/inc1.v:99:       $display(DS<"DS<na>: \"DS<right_side>\"">);
verilog/inc1.v:100:       $display(DS<"prep ( midp1 DS<left_side> midp2 ( outp ) ): \"DS<right_side>\"">);
verilog/inc1.v:101:       $display(DS<"DS<na>: \"DS<na>DS<na>\"">);
verilog/inc1.v:102: COMMENT: /*CMT*/
verilog/inc1.v:102: COMMENT: /*CMT*/
verilog/inc1.v:102: COMMENT: // Results vary between simulators
verilog/inc1.v:102:       $display(DS<"DS<DS<left_side> DS<right_side>	  /*CMT*/  >: \"DS<DS<left_side> DS<right_side>	  /*CMT*/  >\"">);    /*CMT*/  
verilog/inc1.v:103: COMMENT: // Empty
verilog/inc1.v:103:       $display(DS<"DS<>: \"\"">);   /*CMT*/  
verilog/inc1.v:104:       $display(DS<"DS<left side>: \"DS<right side>\"">);
verilog/inc1.v:105:       $display(DS<"DS<left side>: \"DS<right side>\"">);
verilog/inc1.v:106:       $display("standalone");
verilog/inc1.v:107: 
verilog/inc1.v:108: COMMENT: // Unspecified when the stringification has multiple lines
verilog/inc1.v:108:        /*CMT*/  
verilog/inc1.v:109:  
verilog/inc1.v:109: 
verilog/inc1.v:111:       $display(DS<"twoline: \"DS<first        second>\"">);
verilog/inc1.v:112: COMMENT: //$display(`msg(left side, \ right side \ ));  // Not sure \{space} is legal.
verilog/inc1.v:112:        /*CMT*/  
verilog/inc1.v:113:       $write("*-* All Finished *-*\n");
verilog/inc1.v:114:       $finish;
verilog/inc1.v:115:    end
verilog/inc1.v:116: endmodule
verilog/inc1.v:117: 
verilog/inc1.v:118: COMMENT: //======================================================================
verilog/inc1.v:118:  /*CMT*/  
verilog/inc1.v:119: COMMENT: // rt.cpan.org bug34429
verilog/inc1.v:119:  /*CMT*/  
verilog/inc1.v:120: 
verilog/inc1.v:121:  
verilog/inc1.v:121: 
verilog/inc1.v:121: 
verilog/inc1.v:121: 
verilog/inc1.v:125: 
verilog/inc1.v:126: module add1 ( input wire d1, output wire o1);
verilog/inc1.v:127:  DS<
verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0
verilog/inc1.v:127: wire  tmp_d1 = d1; 
verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0
verilog/inc1.v:127: wire  tmp_o1 = tmp_d1 + 1; 
verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0
verilog/inc1.v:127: COMMENT: // expansion is OK
verilog/inc1.v:127: assign o1 = tmp_o1 ;>    /*CMT*/  
verilog/inc1.v:128: endmodule
verilog/inc1.v:129: module add2 ( input wire d2, output wire o2);
verilog/inc1.v:130:  DS<
verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0
verilog/inc1.v:130: wire  tmp_d2 = d2; 
verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0
verilog/inc1.v:130: wire  tmp_o2 = tmp_d2 + 1; 
verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0
verilog/inc1.v:130: COMMENT: // expansion is bad
verilog/inc1.v:130: assign o2 = tmp_o2 ;>   /*CMT*/  
verilog/inc1.v:131: endmodule
verilog/inc1.v:132: 
verilog/inc1.v:133:   
verilog/inc1.v:133: 
verilog/inc1.v:133: 
verilog/inc1.v:133: 
verilog/inc1.v:133: 
verilog/inc1.v:138: 
verilog/inc1.v:139: COMMENT: // parameterized macro with arguments that are macros
verilog/inc1.v:139:  /*CMT*/  
verilog/inc1.v:140:   
verilog/inc1.v:141:   
verilog/inc1.v:142:   
verilog/inc1.v:143: 
verilog/inc1.v:144:    DS<
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144:    generate for (i=0; i<(3); i=i+1) begin 
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144:       psl cover {  DS<DS<m5k.f> .ctl>._ctl_mvldx_m1.d[i] & ~DS<DS<m5k.f> .ctl>._ctl_mvldx_m1.q[i] & !DS<DS<m5k.f> .ctl>._ctl_mvldx_m1.cond & (DS<(DS<DS<m5k.f> .ctl>.alive & DS<DS<m5k.f> .ctl>.alive_m1)>)} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; 
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144:       psl cover { ~DS<DS<m5k.f> .ctl>._ctl_mvldx_m1.d[i] &  DS<DS<m5k.f> .ctl>._ctl_mvldx_m1.q[i] & !DS<DS<m5k.f> .ctl>._ctl_mvldx_m1.cond & (DS<(DS<DS<m5k.f> .ctl>.alive & DS<DS<m5k.f> .ctl>.alive_m1)>)} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; 
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144: COMMENT: // ignorecmt
verilog/inc1.v:144:    end endgenerate>	 /*CMT*/  
verilog/inc1.v:145: 
verilog/inc1.v:146: COMMENT: //======================================================================
verilog/inc1.v:146:  /*CMT*/  
verilog/inc1.v:147: COMMENT: // Quotes are legal in protected blocks.  Grr.
verilog/inc1.v:147:  /*CMT*/  
verilog/inc1.v:148: module prot();
verilog/inc1.v:149: `protected
verilog/inc1.v:149:     I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
verilog/inc1.v:149:     #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
verilog/inc1.v:152: `endprotected
verilog/inc1.v:153: endmodule
verilog/inc1.v:154: COMMENT: //"
verilog/inc1.v:154:  /*CMT*/  
verilog/inc1.v:155: 
verilog/inc1.v:156: COMMENT: //======================================================================
verilog/inc1.v:156:  /*CMT*/  
verilog/inc1.v:157: COMMENT: // macro call with define that has comma
verilog/inc1.v:157:  /*CMT*/  
verilog/inc1.v:158:  
verilog/inc1.v:159:  
verilog/inc1.v:160:  
verilog/inc1.v:161:  
verilog/inc1.v:162:  
verilog/inc1.v:163:  
verilog/inc1.v:164:  
verilog/inc1.v:165: 
verilog/inc1.v:166: DS<begin addr <= ((DS<{DS<regs[DS<6>]>, DS<regs[DS<7>]>}> + 1)); rd <= 1; end> and DS<begin addr <= ((DS<{DS<regs[DS<6>]>, DS<regs[DS<7>]>}>)); wdata <= (rdata); wr <= 1; end>
verilog/inc1.v:167: DS<begin addr <= (DS<{DS<regs[DS<6>]>, DS<regs[DS<7>]>}> + 1); rd <= 1; end>
verilog/inc1.v:168: DS<begin addr <= (DS<{DS<regs[DS<6>]>, DS<regs[DS<7>]>}>); wdata <= (rdata); wr <= 1; end>  more
verilog/inc1.v:169: 
verilog/inc1.v:170: COMMENT: //======================================================================
verilog/inc1.v:170:  /*CMT*/  
verilog/inc1.v:171: COMMENT: // include of parameterized file
verilog/inc1.v:171:  /*CMT*/  
verilog/inc1.v:172:  
verilog/inc1.v:173:  
verilog/inc1.v:173: `line 173 "verilog/inc1.v" 0
verilog/inc1.v:173: `line 1 "verilog/t_preproc_inc4.vh" 1
verilog/t_preproc_inc4.vh:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/t_preproc_inc4.vh:1:  /*CMT*/  
verilog/t_preproc_inc4.vh:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0
verilog/t_preproc_inc4.vh:2:  /*CMT*/  
verilog/t_preproc_inc4.vh:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/t_preproc_inc4.vh:3:  /*CMT*/  
verilog/t_preproc_inc4.vh:4: 
verilog/t_preproc_inc4.vh:5:  
verilog/t_preproc_inc4.vh:6: 
verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2
verilog/inc1.v:173: `line 173 "verilog/inc1.v" 0
verilog/inc1.v:173: 
verilog/inc1.v:174:  
verilog/inc1.v:175:   
verilog/inc1.v:176: 
verilog/inc1.v:177:  
verilog/inc1.v:178: 
verilog/inc1.v:179:  
verilog/inc1.v:180:   
verilog/inc1.v:181: 
verilog/inc1.v:182: 
verilog/inc1.v:183: COMMENT: //======================================================================
verilog/inc1.v:183:  /*CMT*/  
verilog/inc1.v:184: COMMENT: // macro call with , in {}
verilog/inc1.v:184:  /*CMT*/  
verilog/inc1.v:185: 
verilog/inc1.v:186:  
verilog/inc1.v:187: DS<$blah("ab,cd","e,f")>;
verilog/inc1.v:188: DS<$blah(this.logfile,vec)>;
verilog/inc1.v:189: DS<$blah(this.logfile,vec[1,2,3])>;
verilog/inc1.v:190: DS<$blah(this.logfile,{blah.name(), " is not foo"})>;
verilog/inc1.v:191: 
verilog/inc1.v:192: COMMENT: //======================================================================
verilog/inc1.v:192:  /*CMT*/  
verilog/inc1.v:193: COMMENT: // pragma/default net type
verilog/inc1.v:193:  /*CMT*/  
verilog/inc1.v:194: 
verilog/inc1.v:195: `pragma foo = 1
verilog/inc1.v:196: `default_nettype none
verilog/inc1.v:197: `default_nettype uwire
verilog/inc1.v:198: 
verilog/inc1.v:199: COMMENT: //======================================================================
verilog/inc1.v:199:  /*CMT*/  
verilog/inc1.v:200: COMMENT: // Ifdef
verilog/inc1.v:200:  /*CMT*/  
verilog/inc1.v:201: 
verilog/inc1.v:202:  
verilog/inc1.v:203:  
verilog/inc1.v:204:    
verilog/inc1.v:205: 
verilog/inc1.v:206: Line_Preproc_Check 206
verilog/inc1.v:207: 
verilog/inc1.v:208: COMMENT: //======================================================================
verilog/inc1.v:208:  /*CMT*/  
verilog/inc1.v:209: COMMENT: // bug84
verilog/inc1.v:209:  /*CMT*/  
verilog/inc1.v:210: 
verilog/inc1.v:211: COMMENT: // Hello, comments MIGHT not be legal
verilog/inc1.v:211: COMMENT: /*more,,)cmts*/
verilog/inc1.v:212: COMMENT: // But newlines ARE legal... who speced THAT?
verilog/inc1.v:213:   /*CMT*/   /*CMT*/   /*CMT*/  
verilog/inc1.v:213: 
verilog/inc1.v:213: 
verilog/inc1.v:214: DS<(p,q)>
verilog/inc1.v:215: COMMENT: //Here
verilog/inc1.v:215: 
verilog/inc1.v:216: 
verilog/inc1.v:217: COMMENT: //Too
verilog/inc1.v:217: 
verilog/inc1.v:218: COMMENT: /*CMT*/
verilog/inc1.v:218: COMMENT: /*CMT*/
verilog/inc1.v:218: DS<( /*CMT*/    	      x,y     /*CMT*/  )>
verilog/inc1.v:219: Line_Preproc_Check 219
verilog/inc1.v:220: 
verilog/inc1.v:221: COMMENT: //======================================================================
verilog/inc1.v:221:  /*CMT*/  
verilog/inc1.v:222: COMMENT: // defines split arguments
verilog/inc1.v:222:  /*CMT*/  
verilog/inc1.v:223: 
verilog/inc1.v:224:  
verilog/inc1.v:225:  
verilog/inc1.v:226:  
verilog/inc1.v:227:  
verilog/inc1.v:228: COMMENT: // 2001 spec doesn't require two tokens, so "beginend" ok
verilog/inc1.v:228: DS<begin>DS<end>    /*CMT*/  
verilog/inc1.v:229: COMMENT: // 2001 spec doesn't require two tokens, so "beginend" ok
verilog/inc1.v:229: DS<DS<begin>DS<end>>     /*CMT*/  
verilog/inc1.v:230: COMMENT: // No space "beginend"
verilog/inc1.v:230: DS<"DS<begin>DS<end>">   /*CMT*/  
verilog/inc1.v:231: 
verilog/inc1.v:232: COMMENT: //======================================================================
verilog/inc1.v:232:  /*CMT*/  
verilog/inc1.v:233: COMMENT: // bug106
verilog/inc1.v:233:  /*CMT*/  
verilog/inc1.v:234:  
verilog/inc1.v:235:  
verilog/inc1.v:236:   `\esc`def
verilog/inc1.v:237: 
verilog/inc1.v:238: Not a \`define
verilog/inc1.v:239: 
verilog/inc1.v:240: COMMENT: //======================================================================
verilog/inc1.v:240:  /*CMT*/  
verilog/inc1.v:241: COMMENT: // misparsed comma in submacro
verilog/inc1.v:241:  /*CMT*/  
verilog/inc1.v:242:  
verilog/inc1.v:243:  
verilog/inc1.v:244:  
verilog/inc1.v:245:  
verilog/inc1.v:246: DS<DS<x,y)>--DS<bee>>  submacro has comma paren
verilog/inc1.v:247: 
verilog/inc1.v:248: COMMENT: //======================================================================
verilog/inc1.v:248:  /*CMT*/  
verilog/inc1.v:249: COMMENT: // bug191
verilog/inc1.v:249:  /*CMT*/  
verilog/inc1.v:250:  
verilog/inc1.v:251: DS<$display("10 %d %d", $bits(foo), 10);>
verilog/inc1.v:252: 
verilog/inc1.v:253: COMMENT: //======================================================================
verilog/inc1.v:253:  /*CMT*/  
verilog/inc1.v:254: COMMENT: // 1800-2009
verilog/inc1.v:254:  /*CMT*/  
verilog/inc1.v:255:  
verilog/inc1.v:256:     
verilog/inc1.v:257: 
verilog/inc1.v:258:     
verilog/inc1.v:259:     
verilog/inc1.v:260: 
verilog/inc1.v:261: COMMENT: //======================================================================
verilog/inc1.v:261:  /*CMT*/  
verilog/inc1.v:262: COMMENT: // bug202
verilog/inc1.v:262:  /*CMT*/  
verilog/inc1.v:263:  
verilog/inc1.v:263: 
verilog/inc1.v:263: 
verilog/inc1.v:263: 
verilog/inc1.v:263: 
verilog/inc1.v:263: 
verilog/inc1.v:263: 
verilog/inc1.v:263: 
verilog/inc1.v:263: 
verilog/inc1.v:263: 
verilog/inc1.v:263: 
verilog/inc1.v:274: 
verilog/inc1.v:275: DS<
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275:    							
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275:          	
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275:       
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275: 					
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275:   								
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275:      					
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275:           		
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275:     							
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275:      assign a3 = ~b3 ;						
verilog/inc1.v:275: `line 275 "verilog/inc1.v" 0
verilog/inc1.v:275:   >
verilog/inc1.v:276: 
verilog/inc1.v:277: COMMENT: /* multi	\
	 line1*/
verilog/inc1.v:277:  
verilog/inc1.v:277: `line 277 "verilog/inc1.v" 0
verilog/inc1.v:278:  /*CMT*/  	\
verilog/inc1.v:279: 
verilog/inc1.v:279: COMMENT: /*multi	\
	   line2*/
verilog/inc1.v:279:  
verilog/inc1.v:279: `line 279 "verilog/inc1.v" 0
verilog/inc1.v:281:  /*CMT*/  
verilog/inc1.v:281: 
verilog/inc1.v:281: 
verilog/inc1.v:281: 
verilog/inc1.v:281: 
verilog/inc1.v:281: 
verilog/inc1.v:286: 
verilog/inc1.v:286: DS<
verilog/inc1.v:286: `line 286 "verilog/inc1.v" 0
verilog/inc1.v:286: COMMENT: /* multi		
      line 3*/
verilog/inc1.v:286:    
verilog/inc1.v:286: `line 286 "verilog/inc1.v" 0
verilog/inc1.v:286:  /*CMT*/  		
verilog/inc1.v:286: `line 286 "verilog/inc1.v" 0
verilog/inc1.v:286:    def i		
verilog/inc1.v:286: `line 286 "verilog/inc1.v" 0
verilog/inc1.v:286: >
verilog/inc1.v:287: 
verilog/inc1.v:288: COMMENT: //======================================================================
verilog/inc1.v:288:  /*CMT*/  
verilog/inc1.v:289: 
verilog/inc1.v:290: COMMENT: // verilator NOT IN DEFINE
verilog/inc1.v:290:  
verilog/inc1.v:291:  
verilog/inc1.v:292: COMMENT: /* verilator NOT PART
	        OF DEFINE */
verilog/inc1.v:292:  
verilog/inc1.v:293: 
verilog/inc1.v:294:  
verilog/inc1.v:294: 
verilog/inc1.v:296: COMMENT: // CMT NOT
verilog/inc1.v:298:  
verilog/inc1.v:298: 
verilog/inc1.v:298: 
verilog/inc1.v:299: 
verilog/inc1.v:300: COMMENT: /*CMT*/
verilog/inc1.v:300: 1 DS< /*CMT*/  > (nodef)
verilog/inc1.v:301: COMMENT: /* verilator PART OF DEFINE */
verilog/inc1.v:301: 2 DS< /*CMT*/  > (hasdef)
verilog/inc1.v:302: COMMENT: /*CMT*/
verilog/inc1.v:302: 3 DS< /*CMT*/  > (nodef)
verilog/inc1.v:303: COMMENT: /* verilator PART 
	        OF DEFINE */
verilog/inc1.v:303: 4 DS<
verilog/inc1.v:303: `line 303 "verilog/inc1.v" 0
verilog/inc1.v:303:  /*CMT*/  > (nodef)
verilog/inc1.v:304: 5 DS<also in  
verilog/inc1.v:304: `line 304 "verilog/inc1.v" 0
verilog/inc1.v:304: COMMENT: /*CMT*/
verilog/inc1.v:304:   also3    /*CMT*/  > (nodef)
verilog/inc1.v:305:  
verilog/inc1.v:305: 
verilog/inc1.v:307: DS<HAS a NEW 
verilog/inc1.v:307: `line 307 "verilog/inc1.v" 0
verilog/inc1.v:307: LINE>
verilog/inc1.v:308: 
verilog/inc1.v:309: COMMENT: //======================================================================
verilog/inc1.v:309:  /*CMT*/  
verilog/inc1.v:310: 
verilog/inc1.v:311:  
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:311: 
verilog/inc1.v:323: 
verilog/inc1.v:324:  
verilog/inc1.v:325:  
verilog/inc1.v:326: 
verilog/inc1.v:327: EXP: clxx_scen
verilog/inc1.v:328: DS<clxx_scen>
verilog/inc1.v:329: EXP: clxx_scen
verilog/inc1.v:330: DS<"DS<clxx_scen>">
verilog/inc1.v:331:  
verilog/inc1.v:332: EXP: do if (start("verilog/inc1.v", 25)) begin  message({"Blah-", "clx_scen", " end"}); end  while(0);
verilog/inc1.v:333: DS<DS<
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333:    do 
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333: COMMENT: /* synopsys translate_off */
verilog/inc1.v:333:        /*CMT*/   
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333:   
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333:     
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333:  
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333:       if (start("verilog/inc1.v", 333)) begin 
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333:  
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333: 	 message({"Blah-", DS<"DS<clx_scen>">, " end"}); 
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333:       end 
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333: COMMENT: /* synopsys translate_on */
verilog/inc1.v:333:        /*CMT*/   
verilog/inc1.v:333: `line 333 "verilog/inc1.v" 0
verilog/inc1.v:333:    while(0)>;>
verilog/inc1.v:334: 
verilog/inc1.v:335: COMMENT: //======================================================================
verilog/inc1.v:335:  /*CMT*/  
verilog/inc1.v:336: 
verilog/inc1.v:337:  
verilog/inc1.v:337: 
verilog/inc1.v:337: 
verilog/inc1.v:337: 
verilog/inc1.v:341: DS<
verilog/inc1.v:341: `line 341 "verilog/inc1.v" 0
verilog/inc1.v:341:     
verilog/inc1.v:341: `line 341 "verilog/inc1.v" 0
verilog/inc1.v:341:     
verilog/inc1.v:341: `line 341 "verilog/inc1.v" 0
verilog/inc1.v:341: >
verilog/inc1.v:342:      
verilog/inc1.v:343: COMMENT: //`ifndef def_fooed_2  `error "No def_fooed_2" `endif
verilog/inc1.v:343:  /*CMT*/  
verilog/inc1.v:344: EXP: This is fooed
verilog/inc1.v:345: DS<This is fooed>
verilog/inc1.v:346: EXP: This is fooed_2
verilog/inc1.v:347: DS<This is fooed_2>
verilog/inc1.v:348: 
verilog/inc1.v:349: COMMENT: //======================================================================
verilog/inc1.v:349:  /*CMT*/  
verilog/inc1.v:350:  
verilog/inc1.v:351: DS<np>
verilog/inc1.v:352: DS<np>
verilog/inc1.v:353: COMMENT: //======================================================================
verilog/inc1.v:353:  /*CMT*/  
verilog/inc1.v:354: COMMENT: // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution?
verilog/inc1.v:354:  /*CMT*/  
verilog/inc1.v:355:  
verilog/inc1.v:356:  
verilog/inc1.v:357:  
verilog/inc1.v:358:     
verilog/inc1.v:359: 
verilog/inc1.v:360:  
verilog/inc1.v:361:     
verilog/inc1.v:362: 
verilog/inc1.v:363: COMMENT: //======================================================================
verilog/inc1.v:363:  /*CMT*/  
verilog/inc1.v:364: COMMENT: // Metaprogramming
verilog/inc1.v:364:  /*CMT*/  
verilog/inc1.v:365:  
verilog/inc1.v:366:  
verilog/inc1.v:367:  
verilog/inc1.v:368:  
verilog/inc1.v:369:  
verilog/inc1.v:370: 
verilog/inc1.v:371:  
verilog/inc1.v:372:  
verilog/inc1.v:373:  
verilog/inc1.v:374: 
verilog/inc1.v:375: DS<DS<DS<DS<DS<>hello3>>hello3>>hello3>>
verilog/inc1.v:376: DS<DS<DS<DS<DS<hello4>hello4>hello4>hello4>>
verilog/inc1.v:377: COMMENT: //======================================================================
verilog/inc1.v:377:  /*CMT*/  
verilog/inc1.v:378: COMMENT: // Include from stringification
verilog/inc1.v:378:  /*CMT*/  
verilog/inc1.v:379:  
verilog/inc1.v:380:  
verilog/inc1.v:381:  
verilog/inc1.v:381: `line 381 "verilog/inc1.v" 0
verilog/inc1.v:381: `line 1 "verilog/t_preproc_inc4.vh" 1
verilog/t_preproc_inc4.vh:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/t_preproc_inc4.vh:1:  /*CMT*/  
verilog/t_preproc_inc4.vh:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0
verilog/t_preproc_inc4.vh:2:  /*CMT*/  
verilog/t_preproc_inc4.vh:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/t_preproc_inc4.vh:3:  /*CMT*/  
verilog/t_preproc_inc4.vh:4: 
verilog/t_preproc_inc4.vh:5:  
verilog/t_preproc_inc4.vh:6: 
verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2
verilog/inc1.v:381: `line 381 "verilog/inc1.v" 0
verilog/inc1.v:381: 
verilog/inc1.v:382:    
verilog/inc1.v:383: COMMENT: //======================================================================
verilog/inc1.v:383:  /*CMT*/  
verilog/inc1.v:384: COMMENT: // Defines doing defines
verilog/inc1.v:384:  /*CMT*/  
verilog/inc1.v:385: COMMENT: // Note the newline on the end - required to form the end of a define
verilog/inc1.v:385:  /*CMT*/  
verilog/inc1.v:386:  
verilog/inc1.v:386: 
verilog/inc1.v:388:  
verilog/inc1.v:389:  
verilog/inc1.v:390: DS<    DS< 
verilog/inc1.v:390: `line 390 "verilog/inc1.v" 0
verilog/inc1.v:390: > >
verilog/inc1.v:391:      
verilog/inc1.v:392: DS<     >
verilog/inc1.v:393:      
verilog/inc1.v:394: Line_Preproc_Check 394
verilog/inc1.v:395: COMMENT: //======================================================================
verilog/inc1.v:395:  /*CMT*/  
verilog/inc1.v:396: COMMENT: // Quoted multiline - track line numbers, and insure \\n gets propagated
verilog/inc1.v:396:  /*CMT*/  
verilog/inc1.v:397:  
verilog/inc1.v:397: 
verilog/inc1.v:399:  
verilog/inc1.v:400: Line_Preproc_Check 400
verilog/inc1.v:402: 
verilog/inc1.v:402: DS<DS<"FOO \
verilog/inc1.v:402:   BAR "> "arg_line1 \
verilog/inc1.v:402:   arg_line2" DS<"FOO \
verilog/inc1.v:402:   BAR ">>
verilog/inc1.v:403: `line 403 "verilog/inc1.v" 0
verilog/inc1.v:403: Line_Preproc_Check 403
verilog/inc1.v:404: COMMENT: //======================================================================
verilog/inc1.v:404:  /*CMT*/  
verilog/inc1.v:405: COMMENT: // bug283
verilog/inc1.v:405:  /*CMT*/  
verilog/inc1.v:406: 
verilog/inc1.v:407:  
verilog/inc1.v:408:  
verilog/inc1.v:409:  
verilog/inc1.v:410: COMMENT: // EXP: abc
verilog/inc1.v:410:  /*CMT*/  
verilog/inc1.v:411:  
verilog/inc1.v:412: DS<DS<a>``bDS<c>>
verilog/inc1.v:413:  
verilog/inc1.v:414:  
verilog/inc1.v:415:  
verilog/inc1.v:416: 
verilog/inc1.v:417:  
verilog/inc1.v:418:  
verilog/inc1.v:419:  
verilog/inc1.v:420: EXP: sonet_frame
verilog/inc1.v:421: DS<DS<DS<sonet>``_frame>>
verilog/inc1.v:422: COMMENT: //
verilog/inc1.v:422:  /*CMT*/  
verilog/inc1.v:423:  
verilog/inc1.v:424:  
verilog/inc1.v:425: EXP: sonet_frame
verilog/inc1.v:426: DS<DS<sonet_DS<frame>>>
verilog/inc1.v:427: COMMENT: // This result varies between simulators
verilog/inc1.v:427:  /*CMT*/  
verilog/inc1.v:428:  
verilog/inc1.v:429:  
verilog/inc1.v:430: EXP: sonet_frame
verilog/inc1.v:431: DS<DS<sonet>``_frame>
verilog/inc1.v:432: 
verilog/inc1.v:433: COMMENT: // The existance of non-existance of a base define can make a difference
verilog/inc1.v:433:  /*CMT*/  
verilog/inc1.v:434:  
verilog/inc1.v:435:  
verilog/inc1.v:436: EXP: module zzz ; endmodule
verilog/inc1.v:437: module DS<DS<zzz>> ; endmodule
verilog/inc1.v:438: module DS<DS<zzz>> ; endmodule
verilog/inc1.v:439: 
verilog/inc1.v:440:  
verilog/inc1.v:441: EXP: module a_b ; endmodule
verilog/inc1.v:442: module DS<DS<a>``_b> ; endmodule
verilog/inc1.v:443: module DS<DS<a>``_b> ; endmodule
verilog/inc1.v:444: 
verilog/inc1.v:445: COMMENT: //======================================================================
verilog/inc1.v:445:  /*CMT*/  
verilog/inc1.v:446: COMMENT: // bug311
verilog/inc1.v:446:  /*CMT*/  
verilog/inc1.v:447: COMMENT: /*NEED_SPACE*/
verilog/inc1.v:447: integer /*CMT*/  foo;
verilog/inc1.v:448: COMMENT: //======================================================================
verilog/inc1.v:448:  /*CMT*/  
verilog/inc1.v:449: synth_test:
verilog/inc1.v:450: COMMENT: // synopsys translate_off
verilog/inc1.v:450:  /*CMT*/  
verilog/inc1.v:451: synthesis_turned_off
verilog/inc1.v:452: COMMENT: // synthesis translate_on
verilog/inc1.v:452:  /*CMT*/  
verilog/inc1.v:453: EXP: on
verilog/inc1.v:454: COMMENT: //======================================================================
verilog/inc1.v:454:  /*CMT*/  
verilog/inc1.v:455: COMMENT: // bug441
verilog/inc1.v:455:  /*CMT*/  
verilog/inc1.v:456: module t;
verilog/inc1.v:457: COMMENT: //-----
verilog/inc1.v:457:     /*CMT*/  
verilog/inc1.v:458: COMMENT: // case provided
verilog/inc1.v:458:     /*CMT*/  
verilog/inc1.v:459: COMMENT: // note this does NOT escape as suggested in the mail
verilog/inc1.v:459:     /*CMT*/  
verilog/inc1.v:460:  
verilog/inc1.v:461:  
verilog/inc1.v:461: 
verilog/inc1.v:463:    initial begin : DS<\`LEX_CAT(a[0],_assignment)  
verilog/inc1.v:463: `line 463 "verilog/inc1.v" 0
verilog/inc1.v:463: >   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) ");   end
verilog/inc1.v:464: COMMENT: //-----
verilog/inc1.v:464:     /*CMT*/  
verilog/inc1.v:465: COMMENT: // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from
verilog/inc1.v:465:     /*CMT*/  
verilog/inc1.v:466: COMMENT: // substituting and the \ staying in the expansion
verilog/inc1.v:466:     /*CMT*/  
verilog/inc1.v:467: COMMENT: // Note space after name is important so when substitute it has ending whitespace
verilog/inc1.v:467:     /*CMT*/  
verilog/inc1.v:468:  
verilog/inc1.v:468: 
verilog/inc1.v:470:    initial begin : DS<\a[0]_assignment_a[1] 
verilog/inc1.v:470: `line 470 "verilog/inc1.v" 0
verilog/inc1.v:470: >   $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] ");   end
verilog/inc1.v:471:  
verilog/inc1.v:472: COMMENT: //-----
verilog/inc1.v:472:     /*CMT*/  
verilog/inc1.v:473:  
verilog/inc1.v:474:  
verilog/inc1.v:475: COMMENT: // RULE: Ignoring backslash does NOT allow an additional expansion level
verilog/inc1.v:475:     /*CMT*/  
verilog/inc1.v:476: COMMENT: // (Because ESC gets expanded then the \ has it's normal escape meaning)
verilog/inc1.v:476:     /*CMT*/  
verilog/inc1.v:477:    initial begin : DS<\`CAT(pp,suffix)>   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) ");   end
verilog/inc1.v:478:    
verilog/inc1.v:479: COMMENT: //-----
verilog/inc1.v:479:     /*CMT*/  
verilog/inc1.v:480:  
verilog/inc1.v:481:  
verilog/inc1.v:481: 
verilog/inc1.v:483: COMMENT: // Similar to above; \ does not allow expansion after substitution
verilog/inc1.v:483:     /*CMT*/  
verilog/inc1.v:484:    initial begin : DS<\`CAT(ff,bb) 
verilog/inc1.v:484: `line 484 "verilog/inc1.v" 0
verilog/inc1.v:484: >   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) ");   end
verilog/inc1.v:485:    
verilog/inc1.v:486: COMMENT: //-----
verilog/inc1.v:486:     /*CMT*/  
verilog/inc1.v:487:  
verilog/inc1.v:487: 
verilog/inc1.v:489: COMMENT: // MUST: Unknown macro with backslash escape stays as escaped symbol name
verilog/inc1.v:489:     /*CMT*/  
verilog/inc1.v:490:    initial begin : DS<\`zzz 
verilog/inc1.v:490: `line 490 "verilog/inc1.v" 0
verilog/inc1.v:490: >   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz ");   end
verilog/inc1.v:491:  
verilog/inc1.v:492: COMMENT: //-----
verilog/inc1.v:492:     /*CMT*/  
verilog/inc1.v:493:  
verilog/inc1.v:494:  
verilog/inc1.v:494: 
verilog/inc1.v:496: COMMENT: // SHOULD(simulator-dependant): Known macro with backslash escape expands
verilog/inc1.v:496:     /*CMT*/  
verilog/inc1.v:497:    initial begin : DS<\`FOO 
verilog/inc1.v:497: `line 497 "verilog/inc1.v" 0
verilog/inc1.v:497: >    $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO ");  end
verilog/inc1.v:498: COMMENT: // SHOULD(simulator-dependant): Prefix breaks the above
verilog/inc1.v:498:     /*CMT*/  
verilog/inc1.v:499:    initial begin : DS<\xx`FOO 
verilog/inc1.v:499: `line 499 "verilog/inc1.v" 0
verilog/inc1.v:499: >   $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO ");  end
verilog/inc1.v:500:    
verilog/inc1.v:501: COMMENT: //-----
verilog/inc1.v:501:     /*CMT*/  
verilog/inc1.v:502: COMMENT: // MUST: Unknown macro not under call with backslash escape doesn't expand
verilog/inc1.v:502:     /*CMT*/  
verilog/inc1.v:503:  
verilog/inc1.v:504:    initial begin : \`UNKNOWN   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN ");   end
verilog/inc1.v:505: COMMENT: //-----
verilog/inc1.v:505:     /*CMT*/  
verilog/inc1.v:506: COMMENT: // MUST: Unknown macro not under call doesn't expand
verilog/inc1.v:506:     /*CMT*/  
verilog/inc1.v:507:  
verilog/inc1.v:508:    initial begin : \`DEF_NO_EXPAND   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND ");   end
verilog/inc1.v:509:  
verilog/inc1.v:510: COMMENT: //-----
verilog/inc1.v:510:     /*CMT*/  
verilog/inc1.v:511: COMMENT: // bug441 derivative
verilog/inc1.v:511:     /*CMT*/  
verilog/inc1.v:512: COMMENT: // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above)
verilog/inc1.v:512:     /*CMT*/  
verilog/inc1.v:513:  
verilog/inc1.v:514:    initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz");
verilog/inc1.v:515:  
verilog/inc1.v:516: COMMENT: //-----
verilog/inc1.v:516:     /*CMT*/  
verilog/inc1.v:517: COMMENT: // RULE: Because there are quotes after substituting STR, the `A does NOT expand
verilog/inc1.v:517:     /*CMT*/  
verilog/inc1.v:518:  
verilog/inc1.v:519:  
verilog/inc1.v:520:    initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz");
verilog/inc1.v:521:     
verilog/inc1.v:522: endmodule
verilog/inc1.v:523: COMMENT: //======================================================================
verilog/inc1.v:523:  /*CMT*/  
verilog/inc1.v:524: COMMENT: // IEEE mandated predefines
verilog/inc1.v:524:  /*CMT*/  
verilog/inc1.v:525: COMMENT: // undefineall should have no effect on these
verilog/inc1.v:525:    /*CMT*/  
verilog/inc1.v:526: predef DS<0> 0
verilog/inc1.v:527: predef DS<1> 1
verilog/inc1.v:528: predef DS<2> 2
verilog/inc1.v:529: predef DS<3> 3
verilog/inc1.v:530: predef DS<10> 10
verilog/inc1.v:531: predef DS<11> 11
verilog/inc1.v:532: predef DS<20> 20
verilog/inc1.v:533: predef DS<21> 21
verilog/inc1.v:534: predef DS<22> 22
verilog/inc1.v:535: predef DS<23> 23
verilog/inc1.v:536: predef DS<-2> -2
verilog/inc1.v:537: predef DS<-1> -1
verilog/inc1.v:538: predef DS<0> 0
verilog/inc1.v:539: predef DS<1> 1
verilog/inc1.v:540: predef DS<2> 2
verilog/inc1.v:541: 
verilog/inc1.v:542: `line 542 "verilog/inc1.v" 2
