
From: "Mark A. Greer" <mgreer@mvista.com>

This patch adds support for a line of evaluation platforms from Marvell
that use the Marvell GT64260[ab] host bridges.

This patch depends on the Marvell host bridge support patch (mv64x60).

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---

 /dev/null                                   |  798 ----------------------------
 25-akpm/arch/ppc/boot/simple/Makefile       |    2 
 25-akpm/arch/ppc/boot/simple/head.S         |    6 
 25-akpm/arch/ppc/boot/simple/misc-ev64260.S |   82 +-
 25-akpm/arch/ppc/configs/ev64260_defconfig  |  444 ++++++++++-----
 25-akpm/arch/ppc/platforms/Makefile         |    2 
 25-akpm/arch/ppc/platforms/ev64260.c        |  631 ++++++++++++++++++++++
 25-akpm/arch/ppc/platforms/ev64260.h        |  103 ++-
 25-akpm/arch/ppc/syslib/Makefile            |    3 
 9 files changed, 1076 insertions(+), 995 deletions(-)

diff -L arch/ppc/boot/simple/gt64260_tty.c -puN arch/ppc/boot/simple/gt64260_tty.c~ppc32-support-for-marvell-ev-64260-bp-eval-platform /dev/null
--- 25/arch/ppc/boot/simple/gt64260_tty.c
+++ /dev/null	Thu Apr 11 07:25:15 2002
@@ -1,322 +0,0 @@
-/*
- * arch/ppc/boot/simple/gt64260_tty.c
- *
- * Bootloader version of the embedded MPSC/UART driver for the GT64260[A].
- * Note: Due to 64260A errata, DMA will be used for UART input (via SDMA).
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/* This code assumes that the data cache has been disabled (L1, L2, L3). */
-
-#include <linux/config.h>
-#include <linux/serialP.h>
-#include <linux/serial_reg.h>
-#include <asm/serial.h>
-#include <asm/gt64260_defs.h>
-
-extern void udelay(long);
-static void stop_dma(int chan);
-
-static u32	gt64260_base = EV64260_BRIDGE_REG_BASE; /* base addr of 64260 */
-
-inline unsigned
-gt64260_in_le32(volatile unsigned *addr)
-{
-	unsigned ret;
-
-	__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
-				     "r" (addr), "m" (*addr));
-	return ret;
-}
-
-inline void
-gt64260_out_le32(volatile unsigned *addr, int val)
-{
-	__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
-				     "r" (val), "r" (addr));
-}
-
-#define GT64260_REG_READ(offs)						\
-	(gt64260_in_le32((volatile uint *)(gt64260_base + (offs))))
-#define GT64260_REG_WRITE(offs, d)					\
-        (gt64260_out_le32((volatile uint *)(gt64260_base + (offs)), (int)(d)))
-
-
-static struct {
-	u32	sdc;
-	u32	sdcm;
-	u32	rx_desc;
-	u32	rx_buf_ptr;
-	u32	scrdp;
-	u32	tx_desc;
-	u32	sctdp;
-	u32	sftdp;
-} sdma_regs;
-
-#define	SDMA_REGS_INIT(chan) {						\
-	sdma_regs.sdc        = GT64260_SDMA_##chan##_SDC;		\
-	sdma_regs.sdcm       = GT64260_SDMA_##chan##_SDCM;		\
-	sdma_regs.rx_desc    = GT64260_SDMA_##chan##_RX_DESC;		\
-	sdma_regs.rx_buf_ptr = GT64260_SDMA_##chan##_RX_BUF_PTR;	\
-	sdma_regs.scrdp      = GT64260_SDMA_##chan##_SCRDP;		\
-	sdma_regs.tx_desc    = GT64260_SDMA_##chan##_TX_DESC;		\
-	sdma_regs.sctdp      = GT64260_SDMA_##chan##_SCTDP;		\
-	sdma_regs.sftdp      = GT64260_SDMA_##chan##_SFTDP;		\
-}
-
-typedef struct {
-	volatile u16 bufsize;
-	volatile u16 bytecnt;
-	volatile u32 cmd_stat;
-	volatile u32 next_desc_ptr;
-	volatile u32 buffer;
-} gt64260_rx_desc_t;
-
-typedef struct {
-	volatile u16 bytecnt;
-	volatile u16 shadow;
-	volatile u32 cmd_stat;
-	volatile u32 next_desc_ptr;
-	volatile u32 buffer;
-} gt64260_tx_desc_t;
-
-#define	MAX_RESET_WAIT	10000
-#define	MAX_TX_WAIT	10000
-
-#define	RX_NUM_DESC	2
-#define	TX_NUM_DESC	2
-
-#define	RX_BUF_SIZE	16
-#define	TX_BUF_SIZE	16
-
-static gt64260_rx_desc_t rd[RX_NUM_DESC] __attribute__ ((aligned(32)));
-static gt64260_tx_desc_t td[TX_NUM_DESC] __attribute__ ((aligned(32)));
-
-static char rx_buf[RX_NUM_DESC * RX_BUF_SIZE] __attribute__ ((aligned(32)));
-static char tx_buf[TX_NUM_DESC * TX_BUF_SIZE] __attribute__ ((aligned(32)));
-
-static int cur_rd = 0;
-static int cur_td = 0;
-
-
-#define	RX_INIT_RDP(rdp) {						\
-	(rdp)->bufsize = 2;						\
-	(rdp)->bytecnt = 0;						\
-	(rdp)->cmd_stat = GT64260_SDMA_DESC_CMDSTAT_L |			\
-			  GT64260_SDMA_DESC_CMDSTAT_F |			\
-			  GT64260_SDMA_DESC_CMDSTAT_O;			\
-}
-
-unsigned long
-serial_init(int chan, void *ignored)
-{
-	u32	mpsc_adjust, sdma_adjust, brg_bcr;
-	int	i;
-
-	stop_dma(0);
-	stop_dma(1);
-
-	if (chan != 1) {
-		chan = 0;  /* default to chan 0 if anything but 1 */
-		mpsc_adjust = 0;
-		sdma_adjust = 0;
-		brg_bcr = GT64260_BRG_0_BCR;
-		SDMA_REGS_INIT(0);
-	}
-	else {
-		mpsc_adjust = 0x1000;
-		sdma_adjust = 0x2000;
-		brg_bcr = GT64260_BRG_1_BCR;
-		SDMA_REGS_INIT(1);
-	}
-
-	/* Set up ring buffers */
-	for (i=0; i<RX_NUM_DESC; i++) {
-		RX_INIT_RDP(&rd[i]);
-		rd[i].buffer = (u32)&rx_buf[i * RX_BUF_SIZE];
-		rd[i].next_desc_ptr = (u32)&rd[i+1];
-	}
-	rd[RX_NUM_DESC - 1].next_desc_ptr = (u32)&rd[0];
-
-	for (i=0; i<TX_NUM_DESC; i++) {
-		td[i].bytecnt = 0;
-		td[i].shadow = 0;
-		td[i].buffer = (u32)&tx_buf[i * TX_BUF_SIZE];
-		td[i].cmd_stat = GT64260_SDMA_DESC_CMDSTAT_F |
-				 GT64260_SDMA_DESC_CMDSTAT_L;
-		td[i].next_desc_ptr = (u32)&td[i+1];
-	}
-	td[TX_NUM_DESC - 1].next_desc_ptr = (u32)&td[0];
-
-	/* Set MPSC Routing */
-        GT64260_REG_WRITE(GT64260_MPSC_MRR, 0x3ffffe38);
-        GT64260_REG_WRITE(GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
-
-	/* MPSC 0/1 Rx & Tx get clocks BRG0/1 */
-        GT64260_REG_WRITE(GT64260_MPSC_RCRR, 0x00000100);
-        GT64260_REG_WRITE(GT64260_MPSC_TCRR, 0x00000100);
-
-	/* clear pending interrupts */
-        GT64260_REG_WRITE(GT64260_SDMA_INTR_MASK, 0);
-
-	GT64260_REG_WRITE(GT64260_SDMA_0_SCRDP + sdma_adjust, &rd[0]);
-	GT64260_REG_WRITE(GT64260_SDMA_0_SCTDP + sdma_adjust,
-		&td[TX_NUM_DESC - 1]);
-	GT64260_REG_WRITE(GT64260_SDMA_0_SFTDP + sdma_adjust,
-		&td[TX_NUM_DESC - 1]);
-
-	GT64260_REG_WRITE(GT64260_SDMA_0_SDC + sdma_adjust,
-			  GT64260_SDMA_SDC_RFT | GT64260_SDMA_SDC_SFM |
-			  GT64260_SDMA_SDC_BLMR | GT64260_SDMA_SDC_BLMT |
-			  (3 << 12));
-
-	/* Set BRG to generate proper baud rate */
-	GT64260_REG_WRITE(brg_bcr, ((8 << 18) | (1 << 16) | 36));
-
-	/* Put MPSC into UART mode, no null modem, 16x clock mode */
-	GT64260_REG_WRITE(GT64260_MPSC_0_MMCRL + mpsc_adjust, 0x000004c4);
-	GT64260_REG_WRITE(GT64260_MPSC_0_MMCRH + mpsc_adjust, 0x04400400);
-
-        GT64260_REG_WRITE(GT64260_MPSC_0_CHR_1 + mpsc_adjust, 0);
-        GT64260_REG_WRITE(GT64260_MPSC_0_CHR_9 + mpsc_adjust, 0);
-        GT64260_REG_WRITE(GT64260_MPSC_0_CHR_10 + mpsc_adjust, 0);
-        GT64260_REG_WRITE(GT64260_MPSC_0_CHR_3 + mpsc_adjust, 4);
-        GT64260_REG_WRITE(GT64260_MPSC_0_CHR_4 + mpsc_adjust, 0);
-        GT64260_REG_WRITE(GT64260_MPSC_0_CHR_5 + mpsc_adjust, 0);
-        GT64260_REG_WRITE(GT64260_MPSC_0_CHR_6 + mpsc_adjust, 0);
-        GT64260_REG_WRITE(GT64260_MPSC_0_CHR_7 + mpsc_adjust, 0);
-        GT64260_REG_WRITE(GT64260_MPSC_0_CHR_8 + mpsc_adjust, 0);
-
-	/* 8 data bits, 1 stop bit */
-	GT64260_REG_WRITE(GT64260_MPSC_0_MPCR + mpsc_adjust, (3 << 12));
-
-	GT64260_REG_WRITE(GT64260_SDMA_0_SDCM + sdma_adjust,
-		GT64260_SDMA_SDCM_ERD);
-
-	GT64260_REG_WRITE(GT64260_MPSC_0_CHR_2 + sdma_adjust,
-		GT64260_MPSC_UART_CR_EH);
-
-	udelay(100);
-
-	return (ulong)chan;
-}
-
-static void
-stop_dma(int chan)
-{
-	u32	sdma_sdcm = GT64260_SDMA_0_SDCM;
-	int	i;
-
-	if (chan == 1) {
-		sdma_sdcm = GT64260_SDMA_1_SDCM;
-	}
-
-	/* Abort SDMA Rx, Tx */
-	GT64260_REG_WRITE(sdma_sdcm,
-		GT64260_SDMA_SDCM_AR | GT64260_SDMA_SDCM_STD);
-
-	for (i=0; i<MAX_RESET_WAIT; i++) {
-		if ((GT64260_REG_READ(sdma_sdcm) & (GT64260_SDMA_SDCM_AR |
-					GT64260_SDMA_SDCM_AT)) == 0) break;
-		udelay(100);
-	}
-
-	return;
-}
-
-static int
-wait_for_ownership(void)
-{
-	int	i;
-
-	for (i=0; i<MAX_TX_WAIT; i++) {
-		if ((GT64260_REG_READ(sdma_regs.sdcm) &
-					GT64260_SDMA_SDCM_TXD) == 0) break;
-		udelay(1000);
-	}
-
-	return (i < MAX_TX_WAIT);
-}
-
-void
-serial_putc(unsigned long com_port, unsigned char c)
-{
-	gt64260_tx_desc_t	*tdp;
-
-	if (wait_for_ownership() == 0) return;
-
-	tdp = &td[cur_td];
-	if (++cur_td >= TX_NUM_DESC) cur_td = 0;
-
-	*(unchar *)(tdp->buffer ^ 7) = c;
-	tdp->bytecnt = 1;
-	tdp->shadow = 1;
-	tdp->cmd_stat = GT64260_SDMA_DESC_CMDSTAT_L |
-		GT64260_SDMA_DESC_CMDSTAT_F | GT64260_SDMA_DESC_CMDSTAT_O;
-
-	GT64260_REG_WRITE(sdma_regs.sctdp, tdp);
-	GT64260_REG_WRITE(sdma_regs.sftdp, tdp);
-	GT64260_REG_WRITE(sdma_regs.sdcm,
-		GT64260_REG_READ(sdma_regs.sdcm) | GT64260_SDMA_SDCM_TXD);
-
-	return;
-}
-
-unsigned char
-serial_getc(unsigned long com_port)
-{
-	gt64260_rx_desc_t	*rdp;
-	unchar			c = '\0';
-
-	rdp = &rd[cur_rd];
-
-	if ((rdp->cmd_stat & (GT64260_SDMA_DESC_CMDSTAT_O |
-			      GT64260_SDMA_DESC_CMDSTAT_ES)) == 0) {
-		c = *(unchar *)(rdp->buffer ^ 7);
-		RX_INIT_RDP(rdp);
-		if (++cur_rd >= RX_NUM_DESC) cur_rd = 0;
-	}
-
-	return c;
-}
-
-int
-serial_tstc(unsigned long com_port)
-{
-	gt64260_rx_desc_t	*rdp;
-	int			loop_count = 0;
-	int			rc = 0;
-
-	rdp = &rd[cur_rd];
-
-	/* Go thru rcv desc's until empty looking for one with data (no error)*/
-	while (((rdp->cmd_stat & GT64260_SDMA_DESC_CMDSTAT_O) == 0) &&
-	       (loop_count++ < RX_NUM_DESC)) {
-
-		/* If there was an error, reinit the desc & continue */
-		if ((rdp->cmd_stat & GT64260_SDMA_DESC_CMDSTAT_ES) != 0) {
-			RX_INIT_RDP(rdp);
-			if (++cur_rd >= RX_NUM_DESC) cur_rd = 0;
-			rdp = (gt64260_rx_desc_t *)rdp->next_desc_ptr;
-		}
-		else {
-			rc = 1;
-			break;
-		}
-	}
-
-	return rc;
-}
-
-void
-serial_close(unsigned long com_port)
-{
-	stop_dma(com_port);
-	return;
-}
diff -puN arch/ppc/boot/simple/head.S~ppc32-support-for-marvell-ev-64260-bp-eval-platform arch/ppc/boot/simple/head.S
--- 25/arch/ppc/boot/simple/head.S~ppc32-support-for-marvell-ev-64260-bp-eval-platform	Fri Nov 19 16:00:10 2004
+++ 25-akpm/arch/ppc/boot/simple/head.S	Fri Nov 19 16:00:10 2004
@@ -135,9 +135,9 @@ haveOF:
 			 */
 #endif
 
-#ifdef	CONFIG_EV64260
-	/* Move 64260's base regs & CS window for external UART */
-	bl	ev64260_init
+#ifdef	CONFIG_MV64X60
+	/* mv64x60 specific hook to do things like moving register base, etc. */
+	bl	mv64x60_init
 #endif
 
 	/* Get the load address.
diff -puN arch/ppc/boot/simple/Makefile~ppc32-support-for-marvell-ev-64260-bp-eval-platform arch/ppc/boot/simple/Makefile
--- 25/arch/ppc/boot/simple/Makefile~ppc32-support-for-marvell-ev-64260-bp-eval-platform	Fri Nov 19 16:00:10 2004
+++ 25-akpm/arch/ppc/boot/simple/Makefile	Fri Nov 19 16:00:10 2004
@@ -66,7 +66,7 @@ zimageinitrd-$(CONFIG_OCOTEA)		:= zImage
   entrypoint-$(CONFIG_OCOTEA)		:= 0x01000000
      extra.o-$(CONFIG_OCOTEA)		:= pibs.o
 
-     extra.o-$(CONFIG_EV64260)		:= direct.o misc-ev64260.o
+     extra.o-$(CONFIG_EV64260)		:= misc-ev64260.o
          end-$(CONFIG_EV64260)		:= ev64260
    cacheflag-$(CONFIG_EV64260)		:= -include $(clear_L2_L3)
 
diff -puN arch/ppc/boot/simple/misc-ev64260.S~ppc32-support-for-marvell-ev-64260-bp-eval-platform arch/ppc/boot/simple/misc-ev64260.S
--- 25/arch/ppc/boot/simple/misc-ev64260.S~ppc32-support-for-marvell-ev-64260-bp-eval-platform	Fri Nov 19 16:00:10 2004
+++ 25-akpm/arch/ppc/boot/simple/misc-ev64260.S	Fri Nov 19 16:00:10 2004
@@ -6,55 +6,65 @@
  *
  * Author: Mark Greer <mgreer@mvista.com>
  *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ * Copyright 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
  */
 
 #include <asm/ppc_asm.h>
+#include <asm/processor.h>
 #include <asm/cache.h>
-#include <asm/gt64260_defs.h>
-
+#include <asm/mv64x60_defs.h>
 #include <platforms/ev64260.h>
 
-	.globl	ev64260_init
-ev64260_init:
-	li	r20,0
+	.globl	mv64x60_board_init
+mv64x60_board_init:
+	/* DINK doesn't enable 745x timebase, so enable here (Adrian Cox) */
+	mfspr	r25,PVR
+	srwi	r25,r25,16
+	cmplwi	r25,(PVR_7450 >> 16)
+	bne	1f
+	mfspr	r25,HID0
+	oris	r25,r25,(HID0_TBEN >> 16)
+	mtspr	HID0,r25
+1:
+#if (CONFIG_MV64X60_NEW_BASE != CONFIG_MV64X60_BASE)
 	li	r23,20
 
-	/* Relocate galileo's regs */
-        addis	r25,0,GT64260_INTERNAL_SPACE_DEFAULT_ADDR@h
-        ori	r25,r25,GT64260_INTERNAL_SPACE_DECODE
-        lwbrx	r26,0,(r25)
-	lis	r24,0xffff
-	and	r26,r26,r24
-	addis	r24,0,EV64260_BRIDGE_REG_BASE@h
-	srw	r24,r24,r23
-	or	r26,r26,r24
-        stwbrx  r26,0,(r25)
-	sync
-
-	/* Wait for write to take effect */
-        addis	r25,0,EV64260_BRIDGE_REG_BASE@h
-	ori	r25,r25,GT64260_INTERNAL_SPACE_DECODE
-1:	lwbrx	r24,0,(r25)
-	cmpw	r24,r26
-	bne	1b
-
-        /* Change CS2 (UARTS on device module) window */
-        addis	r25,0,EV64260_BRIDGE_REG_BASE@h
-        ori	r25,r25,GT64260_CPU_CS_DECODE_2_BOT
+	/*
+	 * Change the CS2 window for the UART so that the bootloader
+	 * can do I/O thru the UARTs.
+	 */
+	addis	r25,0,CONFIG_MV64X60_NEW_BASE@h
+	ori	r25,r25,MV64x60_CPU2DEV_2_BASE
 	addis	r26,0,EV64260_UART_BASE@h
 	srw	r26,r26,r23
-        stwbrx  r26,0,(r25)
+	stwbrx	r26,0,(r25)
 	sync
 
-        addis	r25,0,EV64260_BRIDGE_REG_BASE@h
-        ori	r25,r25,GT64260_CPU_CS_DECODE_2_TOP
+	addis	r25,0,CONFIG_MV64X60_NEW_BASE@h
+	ori	r25,r25,MV64x60_CPU2DEV_2_SIZE
 	addis	r26,0,EV64260_UART_END@h
 	srw	r26,r26,r23
-        stwbrx  r26,0,(r25)
+	stwbrx	r26,0,(r25)
 	sync
+#endif
+	blr
 
-        blr
+#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
+.data
+	.globl	mv64x60_console_baud
+mv64x60_console_baud:
+.long	EV64260_DEFAULT_BAUD
+
+	.globl	mv64x60_mpsc_clk_src
+mv64x60_mpsc_clk_src:
+.long	EV64260_MPSC_CLK_SRC
+
+	.globl	mv64x60_mpsc_clk_freq
+mv64x60_mpsc_clk_freq:
+.long	EV64260_MPSC_CLK_FREQ
+#endif
diff -puN arch/ppc/configs/ev64260_defconfig~ppc32-support-for-marvell-ev-64260-bp-eval-platform arch/ppc/configs/ev64260_defconfig
--- 25/arch/ppc/configs/ev64260_defconfig~ppc32-support-for-marvell-ev-64260-bp-eval-platform	Fri Nov 19 16:00:10 2004
+++ 25-akpm/arch/ppc/configs/ev64260_defconfig	Fri Nov 19 16:00:10 2004
@@ -1,26 +1,49 @@
 #
 # Automatically generated make config: don't edit
+# Linux kernel version: 2.6.10-rc2
+# Fri Nov 19 11:17:02 2004
 #
 CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
 
 #
 # Code maturity level options
 #
 CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
 
 #
 # General setup
 #
+CONFIG_LOCALVERSION=""
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
 CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
 # CONFIG_EMBEDDED is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
 
 #
 # Loadable module support
@@ -30,31 +53,38 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
 
 #
-# Platform support
+# Processor
 #
-CONFIG_PPC=y
-CONFIG_PPC32=y
 CONFIG_6xx=y
 # CONFIG_40x is not set
+# CONFIG_44x is not set
 # CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
 # CONFIG_8xx is not set
+# CONFIG_E500 is not set
+CONFIG_ALTIVEC=y
+CONFIG_TAU=y
+# CONFIG_TAU_INT is not set
+# CONFIG_TAU_AVERAGE is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_PPC_GEN550=y
+CONFIG_PPC_STD_MMU=y
+# CONFIG_NOT_COHERENT_CACHE is not set
 
 #
-# IBM 4xx options
+# Platform options
 #
-# CONFIG_8260 is not set
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_PPC_STD_MMU=y
 # CONFIG_PPC_MULTIPLATFORM is not set
 # CONFIG_APUS is not set
-# CONFIG_WILLOW_2 is not set
+# CONFIG_WILLOW is not set
 # CONFIG_PCORE is not set
 # CONFIG_POWERPMC250 is not set
-CONFIG_EV64260=y
 # CONFIG_SPRUCE is not set
+CONFIG_EV64260=y
 # CONFIG_LOPEC is not set
 # CONFIG_MCPN765 is not set
 # CONFIG_MVME5100 is not set
@@ -66,37 +96,37 @@ CONFIG_EV64260=y
 # CONFIG_K2 is not set
 # CONFIG_PAL4 is not set
 # CONFIG_GEMINI is not set
+# CONFIG_EST8260 is not set
+# CONFIG_SBC82xx is not set
+# CONFIG_SBS8260 is not set
+# CONFIG_RPX8260 is not set
+# CONFIG_TQM8260 is not set
+# CONFIG_ADS8272 is not set
+# CONFIG_LITE5200 is not set
 CONFIG_GT64260=y
-CONFIG_SERIAL_CONSOLE_BAUD=115200
-# CONFIG_SMP is not set
-# CONFIG_PREEMPT is not set
-CONFIG_ALTIVEC=y
-CONFIG_TAU=y
-# CONFIG_TAU_INT is not set
-# CONFIG_TAU_AVERAGE is not set
-# CONFIG_CPU_FREQ is not set
+CONFIG_MV64X60=y
 
 #
-# General setup
+# Set bridge options
 #
+CONFIG_MV64X60_BASE=0xf1000000
+CONFIG_MV64X60_NEW_BASE=0xfbe00000
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT is not set
 # CONFIG_HIGHMEM is not set
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_KCORE_ELF=y
 CONFIG_BINFMT_ELF=y
-CONFIG_KERNEL_ELF=y
 CONFIG_BINFMT_MISC=y
-CONFIG_PCI_LEGACY_PROC=y
-CONFIG_PCI_NAMES=y
-# CONFIG_HOTPLUG is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,115200 ip=on"
 
 #
-# Parallel port support
+# Bus options
 #
-# CONFIG_PARPORT is not set
-# CONFIG_PPC601_SYNC_FIX is not set
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttyS0,115200 ip=on"
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LEGACY_PROC=y
+CONFIG_PCI_NAMES=y
 
 #
 # Advanced setup
@@ -113,14 +143,28 @@ CONFIG_TASK_SIZE=0x80000000
 CONFIG_BOOT_LOAD=0x00800000
 
 #
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
 # Memory Technology Devices (MTD)
 #
 # CONFIG_MTD is not set
 
 #
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
 # Plug and Play support
 #
-# CONFIG_PNP is not set
 
 #
 # Block devices
@@ -131,32 +175,45 @@ CONFIG_BOOT_LOAD=0x00800000
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set
 CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=4096
 CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
 
 #
-# Multi-device support (RAID and LVM)
+# IO Schedulers
 #
-# CONFIG_MD is not set
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
 
 #
-# ATA/IDE/MFM/RLL support
+# ATA/ATAPI/MFM/RLL support
 #
 # CONFIG_IDE is not set
 
 #
-# SCSI support
+# SCSI device support
 #
 # CONFIG_SCSI is not set
 
 #
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
 # Fusion MPT device support
 #
 
 #
-# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+# IEEE 1394 (FireWire) support
 #
 # CONFIG_IEEE1394 is not set
 
@@ -166,6 +223,10 @@ CONFIG_BLK_DEV_INITRD=y
 # CONFIG_I2O is not set
 
 #
+# Macintosh device drivers
+#
+
+#
 # Networking support
 #
 CONFIG_NET=y
@@ -176,8 +237,6 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 # CONFIG_NETLINK_DEV is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
@@ -191,68 +250,81 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_NET_IPGRE is not set
 # CONFIG_IP_MROUTE is not set
 # CONFIG_ARPD is not set
-# CONFIG_INET_ECN is not set
 CONFIG_SYN_COOKIES=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
 
 #
 # IP: Netfilter Configuration
 #
 # CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
 # CONFIG_IP_NF_QUEUE is not set
 # CONFIG_IP_NF_IPTABLES is not set
 # CONFIG_IP_NF_ARPTABLES is not set
 # CONFIG_IP_NF_COMPAT_IPCHAINS is not set
 # CONFIG_IP_NF_COMPAT_IPFWADM is not set
-# CONFIG_IPV6 is not set
-# CONFIG_XFRM_USER is not set
 
 #
 # SCTP Configuration (EXPERIMENTAL)
 #
-CONFIG_IPV6_SCTP__=y
 # CONFIG_IP_SCTP is not set
 # CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
-# CONFIG_LLC is not set
 # CONFIG_DECNET is not set
-# CONFIG_BRIDGE is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
 # CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_HW_FLOWCONTROL is not set
 
 #
 # QoS and/or fair queueing
 #
 # CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
 CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
 
 #
 # ARCnet devices
 #
 # CONFIG_ARCNET is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
 #
 CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
-# CONFIG_OAKNET is not set
+CONFIG_MII=y
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
@@ -260,17 +332,26 @@ CONFIG_NET_ETHERNET=y
 #
 # Tulip family network device support
 #
-# CONFIG_NET_TULIP is not set
+CONFIG_NET_TULIP=y
+# CONFIG_DE2104X is not set
+CONFIG_TULIP=y
+# CONFIG_TULIP_MWI is not set
+# CONFIG_TULIP_MMIO is not set
+# CONFIG_TULIP_NAPI is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_DM9102 is not set
 # CONFIG_HP100 is not set
 CONFIG_NET_PCI=y
 # CONFIG_PCNET32 is not set
 # CONFIG_AMD8111_ETH is not set
 # CONFIG_ADAPTEC_STARFIRE is not set
 # CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
 # CONFIG_DGRS is not set
-CONFIG_EEPRO100=y
-# CONFIG_EEPRO100_PIO is not set
-# CONFIG_E100 is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_E100_NAPI is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
@@ -293,85 +374,98 @@ CONFIG_EEPRO100=y
 # CONFIG_YELLOWFIN is not set
 # CONFIG_R8169 is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
 # CONFIG_TIGON3 is not set
 
 #
 # Ethernet (10000 Mbit)
 #
 # CONFIG_IXGB is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
+# CONFIG_S2IO is not set
 
 #
-# Wireless LAN (non-hamradio)
+# Token Ring devices
 #
-# CONFIG_NET_RADIO is not set
+# CONFIG_TR is not set
 
 #
-# Token Ring devices (depends on LLC=y)
+# Wireless LAN (non-hamradio)
 #
-# CONFIG_RCPCI is not set
-# CONFIG_SHAPER is not set
+# CONFIG_NET_RADIO is not set
 
 #
 # Wan interfaces
 #
 # CONFIG_WAN is not set
-
-#
-# Amateur Radio support
-#
-# CONFIG_HAMRADIO is not set
-
-#
-# IrDA (infrared) support
-#
-# CONFIG_IRDA is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
 
 #
 # ISDN subsystem
 #
-# CONFIG_ISDN_BOOL is not set
+# CONFIG_ISDN is not set
 
 #
-# Graphics support
+# Telephony Support
 #
-# CONFIG_FB is not set
-
-#
-# Old CD-ROM drivers (not SCSI, not IDE)
-#
-# CONFIG_CD_NO_IDESCSI is not set
+# CONFIG_PHONE is not set
 
 #
 # Input device support
 #
-# CONFIG_INPUT is not set
+CONFIG_INPUT=y
 
 #
 # Userland interfaces
 #
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
 
 #
 # Input I/O drivers
 #
 # CONFIG_GAMEPORT is not set
 CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_RAW is not set
 
 #
 # Input Device Drivers
 #
-
-#
-# Macintosh device drivers
-#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
 
 #
 # Character devices
 #
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -379,6 +473,7 @@ CONFIG_SOUND_GAMEPORT=y
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
 # CONFIG_SERIAL_8250_EXTENDED is not set
 
 #
@@ -387,68 +482,120 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
-CONFIG_UNIX98_PTY_COUNT=256
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
 
 #
 # I2C support
 #
 CONFIG_I2C=m
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Algorithms
+#
 # CONFIG_I2C_ALGOBIT is not set
 # CONFIG_I2C_ALGOPCF is not set
-CONFIG_I2C_CHARDEV=m
+# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C Hardware Sensors Mainboard support
+# I2C Hardware Bus support
 #
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
 # CONFIG_I2C_ALI15X3 is not set
 # CONFIG_I2C_AMD756 is not set
 # CONFIG_I2C_AMD8111 is not set
 # CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_ISA is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_SCx200_ACB is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
 # CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
 # CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
 
 #
-# I2C Hardware Sensors Chip support
+# Hardware Sensors Chip support
 #
+# CONFIG_I2C_SENSOR is not set
 # CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
 # CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
 # CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_W83781D is not set
-# CONFIG_I2C_SENSOR is not set
-
-#
-# Mice
-#
-# CONFIG_BUSMOUSE is not set
-# CONFIG_QIC02_TAPE is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
 
 #
-# IPMI
+# Other I2C Chip support
 #
-# CONFIG_IPMI_HANDLER is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 
 #
-# Watchdog Cards
+# Dallas's 1-wire bus
 #
-# CONFIG_WATCHDOG is not set
-# CONFIG_NVRAM is not set
-CONFIG_GEN_RTC=y
-# CONFIG_GEN_RTC_X is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
+# CONFIG_W1 is not set
 
 #
-# Ftape, the floppy tape device driver
+# Misc devices
 #
-# CONFIG_FTAPE is not set
-# CONFIG_AGP is not set
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_HANGCHECK_TIMER is not set
 
 #
 # Multimedia devices
@@ -461,6 +608,34 @@ CONFIG_GEN_RTC=y
 # CONFIG_DVB is not set
 
 #
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
@@ -473,6 +648,7 @@ CONFIG_EXT2_FS=y
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
 # CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 
@@ -485,19 +661,23 @@ CONFIG_EXT2_FS=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
 # CONFIG_NTFS_FS is not set
 
 #
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_SYSFS=y
 CONFIG_DEVFS_FS=y
 # CONFIG_DEVFS_MOUNT is not set
 # CONFIG_DEVFS_DEBUG is not set
-CONFIG_DEVPTS_FS=y
 # CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 
 #
@@ -506,6 +686,7 @@ CONFIG_RAMFS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
@@ -522,18 +703,19 @@ CONFIG_RAMFS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
 # CONFIG_NFSD is not set
 CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 # CONFIG_EXPORTFS is not set
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_GSS is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
-# CONFIG_INTERMEZZO_FS is not set
 # CONFIG_AFS_FS is not set
 
 #
@@ -543,36 +725,32 @@ CONFIG_SUNRPC=y
 CONFIG_MSDOS_PARTITION=y
 
 #
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# USB support
+# Native Language Support
 #
-# CONFIG_USB is not set
-# CONFIG_USB_GADGET is not set
+# CONFIG_NLS is not set
 
 #
-# Bluetooth support
+# Library routines
 #
-# CONFIG_BT is not set
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
 
 #
-# Library routines
+# Profiling support
 #
-# CONFIG_CRC32 is not set
+# CONFIG_PROFILING is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_DEBUG_KERNEL is not set
-# CONFIG_KALLSYMS is not set
 # CONFIG_SERIAL_TEXT_DEBUG is not set
 
 #
 # Security options
 #
+# CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 
 #
diff -puN /dev/null arch/ppc/platforms/ev64260.c
--- /dev/null	Thu Apr 11 07:25:15 2002
+++ 25-akpm/arch/ppc/platforms/ev64260.c	Fri Nov 19 16:00:10 2004
@@ -0,0 +1,631 @@
+/*
+ * arch/ppc/platforms/ev64260.c
+ *
+ * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2001-2003 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * The EV-64260-BP port is the result of hard work from many people from
+ * many companies.  In particular, employees of Marvell/Galileo, Mission
+ * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
+ *
+ * Note: I have not been able to get *all* PCI slots to work reliably
+ *	at 66 MHz.  I recommend setting jumpers J15 & J16 to short pins 1&2
+ *	so that 33 MHz is used. --MAG
+ * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK.
+ * 	At 100MHz, they are solid.
+ */
+#include <linux/config.h>
+
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/ide.h>
+#include <linux/irq.h>
+#include <linux/fs.h>
+#include <linux/seq_file.h>
+#include <linux/console.h>
+#include <linux/initrd.h>
+#include <linux/root_dev.h>
+#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+#else
+#include <linux/mv643xx.h>
+#endif
+#include <asm/bootinfo.h>
+#include <asm/machdep.h>
+#include <asm/mv64x60.h>
+#include <asm/todc.h>
+#include <asm/time.h>
+
+#include <platforms/ev64260.h>
+
+#define BOARD_VENDOR	"Marvell/Galileo"
+#define BOARD_MACHINE	"EV-64260-BP"
+
+static struct mv64x60_handle	bh;
+
+#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
+extern void gen550_progress(char *, unsigned short);
+extern void gen550_init(int, struct uart_port *);
+#endif
+
+static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
+	18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
+};
+static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */
+	{ 1, 15, 14,  2,  4, 13,  5,  9,  6, 11,  8, 10, 16, 12,  7,  0 },
+	{ 0, 30,  0,  2,  0, 26,  0, 18,  0, 22, 20, 24, 28, 32,  0,  0 }
+};
+
+
+TODC_ALLOC();
+
+static int
+ev64260_get_bus_speed(void)
+{
+	return 100000000;
+}
+
+static int
+ev64260_get_cpu_speed(void)
+{
+	unsigned long	pvr, hid1, pll_ext;
+
+	pvr = PVR_VER(mfspr(PVR));
+
+	if (pvr != PVR_VER(PVR_7450)) {
+		hid1 = mfspr(HID1) >> 28;
+		return ev64260_get_bus_speed() * cpu_7xx[hid1]/2;
+	}
+	else {
+		hid1 = (mfspr(HID1) & 0x0001e000) >> 13;
+		pll_ext = 0; /* No way to read; must get from schematic */
+		return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2;
+	}
+}
+
+unsigned long __init
+ev64260_find_end_of_memory(void)
+{
+	return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
+		MV64x60_TYPE_GT64260A);
+}
+
+/*
+ * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
+ * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first
+ *	PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ).
+ *	This is the most IRQs you can get from one bus with this board, though.
+ */
+static int __init
+ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+	struct pci_controller	*hose = pci_bus_to_hose(dev->bus->number);
+
+	if (hose->index == 0) {
+		static char pci_irq_table[][4] =
+		/*
+		 *	PCI IDSEL/INTPIN->INTLINE
+		 * 	   A   B   C   D
+		 */
+		{
+			{EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */
+			{EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */
+		};
+
+		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
+		return PCI_IRQ_TABLE_LOOKUP;
+	}
+	else {
+		static char pci_irq_table[][4] =
+		/*
+		 *	PCI IDSEL/INTPIN->INTLINE
+		 * 	   A   B   C   D
+		 */
+		{
+			{ EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */
+			{ EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */
+		};
+
+		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
+		return PCI_IRQ_TABLE_LOOKUP;
+	}
+}
+
+static void __init
+ev64260_setup_peripherals(void)
+{
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
+		EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0);
+	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
+		EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0);
+	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
+		EV64260_TODC_BASE, EV64260_TODC_SIZE, 0);
+	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
+		EV64260_UART_BASE, EV64260_UART_SIZE, 0);
+	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
+		EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0);
+	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
+
+	TODC_INIT(TODC_TYPE_DS1501, 0, 0,
+			ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8);
+
+	mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29)));
+	mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27));
+
+	if (ev64260_get_bus_speed() > 100000000)
+		mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23));
+
+	mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
+	mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
+
+        /*
+         * Enabling of PCI internal-vs-external arbitration
+         * is a platform- and errata-dependent decision.
+         */
+        if (bh.type == MV64x60_TYPE_GT64260A )  {
+                mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
+                mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
+        }
+
+        mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
+
+	/*
+	 * Turn off timer/counters.  Not turning off watchdog timer because
+	 * can't read its reg on the 64260A so don't know if we'll be enabling
+	 * or disabling.
+	 */
+	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
+			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
+	mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
+			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
+
+	/*
+	 * Set MPSC Multiplex RMII
+	 * NOTE: ethernet driver modifies bit 0 and 1
+	 */
+	mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
+
+	/*
+	 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
+	 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
+	 * register).  Need to route the MPP inputs to the GPP and set the
+	 * polarity correctly.
+	 *
+	 * In MPP Control 2 Register
+	 *   MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0
+	 *   MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0
+	 */
+	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) );
+
+	/*
+	 * In MPP Control 3 Register
+	 *   MPP 26 -> GPP 26 (RTC INT)		bits  8-11 -> 0
+	 *   MPP 27 -> GPP 27 (PCI 0 INTA)	bits 12-15 -> 0
+	 *   MPP 29 -> GPP 29 (PCI 1 INTA)	bits 20-23 -> 0
+	 */
+	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20));
+
+#define GPP_EXTERNAL_INTERRUPTS \
+		((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29))
+	/* DUART & PCI interrupts are inputs */
+	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
+	/* DUART & PCI interrupts are active low */
+	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
+
+	/* Clear any pending interrupts for these inputs and enable them. */
+	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
+	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
+
+	return;
+}
+
+static void __init
+ev64260_setup_bridge(void)
+{
+	struct mv64x60_setup_info	si;
+	int				i;
+
+	memset(&si, 0, sizeof(si));
+
+	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
+
+	si.pci_0.enable_bus = 1;
+	si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE;
+	si.pci_0.pci_io.pci_base_hi = 0;
+	si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE;
+	si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE;
+	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
+	si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE;
+	si.pci_0.pci_mem[0].pci_base_hi = 0;
+	si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE;
+	si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE;
+	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
+	si.pci_0.pci_cmd_bits = 0;
+	si.pci_0.latency_timer = 0x8;
+
+	si.pci_1.enable_bus = 1;
+	si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE;
+	si.pci_1.pci_io.pci_base_hi = 0;
+	si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE;
+	si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE;
+	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
+	si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE;
+	si.pci_1.pci_mem[0].pci_base_hi = 0;
+	si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE;
+	si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE;
+	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
+	si.pci_1.pci_cmd_bits = 0;
+	si.pci_1.latency_timer = 0x8;
+
+	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
+		si.cpu_prot_options[i] = 0;
+		si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
+		si.pci_0.acc_cntl_options[i] =
+			GT64260_PCI_ACC_CNTL_DREADEN |
+			GT64260_PCI_ACC_CNTL_RDPREFETCH |
+			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
+			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
+			GT64260_PCI_ACC_CNTL_SWAP_NONE |
+			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
+		si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
+		si.pci_1.acc_cntl_options[i] =
+			GT64260_PCI_ACC_CNTL_DREADEN |
+			GT64260_PCI_ACC_CNTL_RDPREFETCH |
+			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
+			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
+			GT64260_PCI_ACC_CNTL_SWAP_NONE |
+			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
+		si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
+	}
+
+        /* Lookup PCI host bridges */
+        if (mv64x60_init(&bh, &si))
+                printk("Bridge initialization failed.\n");
+
+	pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
+	ppc_md.pci_swizzle = common_swizzle;
+	ppc_md.pci_map_irq = ev64260_map_irq;
+	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
+
+	mv64x60_set_bus(&bh, 0, 0);
+	bh.hose_a->first_busno = 0;
+	bh.hose_a->last_busno = 0xff;
+	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
+
+	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
+	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
+	bh.hose_b->last_busno = 0xff;
+	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
+		bh.hose_b->first_busno);
+
+	return;
+}
+
+#if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE)
+static void __init
+ev64260_early_serial_map(void)
+{
+	struct uart_port	port;
+	static char		first_time = 1;
+
+	if (first_time) {
+		memset(&port, 0, sizeof(port));
+
+		port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE);
+		port.irq = EV64260_UART_0_IRQ;
+		port.uartclk = BASE_BAUD * 16;
+		port.regshift = 2;
+		port.iotype = SERIAL_IO_MEM;
+		port.flags = STD_COM_FLAGS;
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+		gen550_init(0, &port);
+#endif
+
+		if (early_serial_setup(&port) != 0)
+			printk("Early serial init of port 0 failed\n");
+
+		first_time = 0;
+	}
+
+	return;
+}
+#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
+static void __init
+ev64260_early_serial_map(void)
+{
+}
+#endif
+
+static int __init
+ev64260_fixup_pd(void)
+{
+#if defined(CONFIG_SERIAL_MPSC)
+	struct list_head	*entry;
+	struct platform_device	*pd;
+	struct device		*dev;
+	struct mpsc_pd_dd	*dd;
+
+	list_for_each(entry, &platform_bus_type.devices.list) {
+		dev = container_of(entry, struct device, bus_list);
+		pd = container_of(dev, struct platform_device, dev);
+
+		if (!strncmp(pd->name, MPSC_CTLR_NAME, BUS_ID_SIZE)) {
+			dd = (struct mpsc_pd_dd *) dev_get_drvdata(&pd->dev);
+
+			dd->max_idle = 40;
+			dd->default_baud = EV64260_DEFAULT_BAUD;
+			dd->brg_clk_src = EV64260_MPSC_CLK_SRC;
+			dd->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
+		}
+	}
+#endif
+
+	return 0;
+}
+
+subsys_initcall(ev64260_fixup_pd);
+
+static void __init
+ev64260_setup_arch(void)
+{
+	if (ppc_md.progress)
+		ppc_md.progress("ev64260_setup_arch: enter", 0);
+
+#ifdef CONFIG_BLK_DEV_INITRD
+	if (initrd_start)
+		ROOT_DEV = Root_RAM0;
+	else
+#endif
+#ifdef	CONFIG_ROOT_NFS
+		ROOT_DEV = Root_NFS;
+#else
+		ROOT_DEV = Root_SDA2;
+#endif
+
+	if (ppc_md.progress)
+		ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0);
+
+	/* Enable L2 and L3 caches (if 745x) */
+	_set_L2CR(_get_L2CR() | L2CR_L2E);
+	_set_L3CR(_get_L3CR() | L3CR_L3E);
+
+	if (ppc_md.progress)
+		ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0);
+
+	ev64260_setup_bridge();		/* set up PCI bridge(s) */
+	ev64260_setup_peripherals();	/* set up chip selects/GPP/MPP etc */
+
+	if (ppc_md.progress)
+		ppc_md.progress("ev64260_setup_arch: bridge init complete", 0);
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
+	ev64260_early_serial_map();
+#endif
+
+	printk(BOARD_VENDOR " " BOARD_MACHINE "\n");
+	printk("EV-64260-BP port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
+
+	if (ppc_md.progress)
+		ppc_md.progress("ev64260_setup_arch: exit", 0);
+
+	return;
+}
+
+static void
+ev64260_reset_board(void *addr)
+{
+	local_irq_disable();
+
+	/* disable and invalidate the L2 cache */
+	_set_L2CR(0);
+	_set_L2CR(0x200000);
+
+	/* flush and disable L1 I/D cache */
+	__asm__ __volatile__
+	("mfspr   3,1008\n\t"
+	 "ori	5,5,0xcc00\n\t"
+	 "ori	4,3,0xc00\n\t"
+	 "andc	5,3,5\n\t"
+	 "sync\n\t"
+	 "mtspr	1008,4\n\t"
+	 "isync\n\t"
+	 "sync\n\t"
+	 "mtspr	1008,5\n\t"
+	 "isync\n\t"
+	 "sync\n\t");
+
+	/* unmap any other random cs's that might overlap with bootcs */
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0);
+	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0);
+	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0);
+	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0);
+	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
+
+	/* map bootrom back in to gt @ reset defaults */
+	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
+						0xff800000, 8*1024*1024, 0);
+	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
+
+	/* move reg base back to default, setup default pci0 */
+	mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE,
+		(1<<24) | CONFIG_MV64X60_BASE >> 20);
+
+	/* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped
+	 * via BAT or MMU, and MSR IR/DR is ON */
+	/* SRR0 has system reset vector, SRR1 has default MSR value */
+	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
+	/* NOTE: assumes reset vector is at 0xfff00100 */
+	__asm__ __volatile__
+	("mtspr   26, %0\n\t"
+	 "li      4,(1<<6)\n\t"
+	 "mtspr   27,4\n\t"
+	 "rfi\n\t"
+	 :: "r" (addr):"r4");
+
+	return;
+}
+
+static void
+ev64260_restart(char *cmd)
+{
+	volatile ulong	i = 10000000;
+
+	ev64260_reset_board((void *)0xfff00100);
+
+	while (i-- > 0);
+	panic("restart failed\n");
+}
+
+static void
+ev64260_halt(void)
+{
+	local_irq_disable();
+	while (1);
+	/* NOTREACHED */
+}
+
+static void
+ev64260_power_off(void)
+{
+	ev64260_halt();
+	/* NOTREACHED */
+}
+
+static int
+ev64260_show_cpuinfo(struct seq_file *m)
+{
+	uint pvid;
+
+	pvid = mfspr(PVR);
+	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
+	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
+	seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000);
+	seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000);
+
+	return 0;
+}
+
+/* DS1501 RTC has too much variation to use RTC for calibration */
+static void __init
+ev64260_calibrate_decr(void)
+{
+	ulong freq;
+
+	freq = ev64260_get_bus_speed()/4;
+
+	printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
+	       freq/1000000, freq%1000000);
+
+	tb_ticks_per_jiffy = freq / HZ;
+	tb_to_us = mulhwu_scale_factor(freq, 1000000);
+
+	return;
+}
+
+/*
+ * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space.
+ */
+static __inline__ void
+ev64260_set_bat(void)
+{
+	mb();
+	mtspr(DBAT1U, 0xfb0001fe);
+	mtspr(DBAT1L, 0xfb00002a);
+	mb();
+
+	return;
+}
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+static void __init
+ev64260_map_io(void)
+{
+	io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO);
+}
+#endif
+
+void __init
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
+{
+#ifdef CONFIG_BLK_DEV_INITRD
+	extern int	initrd_below_start_ok;
+
+	initrd_start=initrd_end=0;
+	initrd_below_start_ok=0;
+#endif /* CONFIG_BLK_DEV_INITRD */
+
+	parse_bootinfo(find_bootinfo());
+
+	isa_mem_base = 0;
+	isa_io_base = EV64260_PCI0_IO_CPU_BASE;
+	pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE;
+
+	loops_per_jiffy = ev64260_get_cpu_speed() / HZ;
+
+	ppc_md.setup_arch = ev64260_setup_arch;
+	ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
+	ppc_md.init_IRQ = gt64260_init_irq;
+	ppc_md.get_irq = gt64260_get_irq;
+
+	ppc_md.restart = ev64260_restart;
+	ppc_md.power_off = ev64260_power_off;
+	ppc_md.halt = ev64260_halt;
+
+	ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
+
+	ppc_md.init = NULL;
+
+	ppc_md.time_init = todc_time_init;
+	ppc_md.set_rtc_time = todc_set_rtc_time;
+	ppc_md.get_rtc_time = todc_get_rtc_time;
+	ppc_md.nvram_read_val = todc_direct_read_val;
+	ppc_md.nvram_write_val = todc_direct_write_val;
+	ppc_md.calibrate_decr = ev64260_calibrate_decr;
+
+	bh.p_base = CONFIG_MV64X60_NEW_BASE;
+
+	ev64260_set_bat();
+
+#ifdef	CONFIG_SERIAL_8250
+#if defined(CONFIG_SERIAL_TEXT_DEBUG)
+	ppc_md.setup_io_mappings = ev64260_map_io;
+	ppc_md.progress = gen550_progress;
+#endif
+#if defined(CONFIG_KGDB)
+	ppc_md.setup_io_mappings = ev64260_map_io;
+	ppc_md.early_serial_map = ev64260_early_serial_map;
+#endif
+#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
+#ifdef	CONFIG_SERIAL_TEXT_DEBUG
+	ppc_md.setup_io_mappings = ev64260_map_io;
+	ppc_md.progress = mv64x60_mpsc_progress;
+	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
+#endif	/* CONFIG_SERIAL_TEXT_DEBUG */
+#ifdef	CONFIG_KGDB
+	ppc_md.setup_io_mappings = ev64260_map_io;
+	ppc_md.early_serial_map = ev64260_early_serial_map;
+#endif	/* CONFIG_KGDB */
+
+#endif
+
+	return;
+}
diff -puN arch/ppc/platforms/ev64260.h~ppc32-support-for-marvell-ev-64260-bp-eval-platform arch/ppc/platforms/ev64260.h
--- 25/arch/ppc/platforms/ev64260.h~ppc32-support-for-marvell-ev-64260-bp-eval-platform	Fri Nov 19 16:00:10 2004
+++ 25-akpm/arch/ppc/platforms/ev64260.h	Fri Nov 19 16:00:10 2004
@@ -5,38 +5,103 @@
  *
  * Author: Mark A. Greer <mgreer@mvista.com>
  *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
+ * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
  * the terms of the GNU General Public License version 2.  This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
  */
 
 /*
- * The GT64260 has 2 PCI buses each with 1 window from the CPU bus to
+ * The MV64x60 has 2 PCI buses each with 1 window from the CPU bus to
  * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
  * We'll only use one PCI MEM window on each PCI bus.
+ *
+ * This is the CPU physical memory map (windows must be at least 1MB and start
+ * on a boundary that is a multiple of the window size):
+ *
+ * 	0xfc000000-0xffffffff		- External FLASH on device module
+ * 	0xfbf00000-0xfbffffff		- Embedded (on board) FLASH
+ * 	0xfbe00000-0xfbefffff		- GT64260 Registers (preferably)
+ * 					  but really a config option
+ * 	0xfbd00000-0xfbdfffff		- External SRAM on device module
+ * 	0xfbc00000-0xfbcfffff		- TODC chip on device module
+ * 	0xfbb00000-0xfbbfffff		- External UART on device module
+ * 	0xa2000000-0xfbafffff		- <hole>
+ * 	0xa1000000-0xa1ffffff		- PCI 1 I/O (defined in gt64260.h)
+ * 	0xa0000000-0xa0ffffff		- PCI 0 I/O (defined in gt64260.h)
+ * 	0x90000000-0x9fffffff		- PCI 1 MEM (defined in gt64260.h)
+ * 	0x80000000-0x8fffffff		- PCI 0 MEM (defined in gt64260.h)
  */
 
 #ifndef __PPC_PLATFORMS_EV64260_H
 #define __PPC_PLATFORMS_EV64260_H
 
-#define	EV64260_BRIDGE_REG_BASE		0xf8000000
-#define	EV64260_BRIDGE_REG_BASE_TO_TOP	0x08000000U
+/* PCI mappings */
+#define	EV64260_PCI0_IO_CPU_BASE	0xa0000000
+#define	EV64260_PCI0_IO_PCI_BASE	0x00000000
+#define	EV64260_PCI0_IO_SIZE		0x01000000
+
+#define	EV64260_PCI0_MEM_CPU_BASE	0x80000000
+#define	EV64260_PCI0_MEM_PCI_BASE	0x80000000
+#define	EV64260_PCI0_MEM_SIZE		0x10000000
+
+#define	EV64260_PCI1_IO_CPU_BASE	(EV64260_PCI0_IO_CPU_BASE + \
+						EV64260_PCI0_IO_SIZE)
+#define	EV64260_PCI1_IO_PCI_BASE	(EV64260_PCI0_IO_PCI_BASE + \
+						EV64260_PCI0_IO_SIZE)
+#define	EV64260_PCI1_IO_SIZE		0x01000000
+
+#define	EV64260_PCI1_MEM_CPU_BASE	(EV64260_PCI0_MEM_CPU_BASE + \
+						EV64260_PCI0_MEM_SIZE)
+#define	EV64260_PCI1_MEM_PCI_BASE	(EV64260_PCI0_MEM_PCI_BASE + \
+						EV64260_PCI0_MEM_SIZE)
+#define	EV64260_PCI1_MEM_SIZE		0x10000000
+
+/* CPU Physical Memory Map setup (other than PCI) */
+#define	EV64260_EXT_FLASH_BASE		0xfc000000
+#define	EV64260_EMB_FLASH_BASE		0xfbf00000
+#define	EV64260_EXT_SRAM_BASE		0xfbd00000
+#define	EV64260_TODC_BASE		0xfbc00000
+#define	EV64260_UART_BASE		0xfbb00000
+
+#define	EV64260_EXT_FLASH_SIZE_ACTUAL	0x04000000  /* <= 64MB Extern FLASH */
+#define	EV64260_EMB_FLASH_SIZE_ACTUAL	0x00080000  /* 512KB of Embed FLASH */
+#define	EV64260_EXT_SRAM_SIZE_ACTUAL	0x00100000  /* 1MB SDRAM */
+#define	EV64260_TODC_SIZE_ACTUAL	0x00000020  /* 32 bytes for TODC */
+#define	EV64260_UART_SIZE_ACTUAL	0x00000040  /* 64 bytes for DUART */
+
+#define	EV64260_EXT_FLASH_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
+						EV64260_EXT_FLASH_SIZE_ACTUAL)
+#define	EV64260_EMB_FLASH_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
+						EV64260_EMB_FLASH_SIZE_ACTUAL)
+#define	EV64260_EXT_SRAM_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
+						EV64260_EXT_SRAM_SIZE_ACTUAL)
+#define	EV64260_TODC_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
+						EV64260_TODC_SIZE_ACTUAL)
+/* Assembler in bootwrapper blows up if 'max' is used */
+#define	EV64260_UART_SIZE		GT64260_WINDOW_SIZE_MIN
+#define	EV64260_UART_END		((EV64260_UART_BASE +		\
+					EV64260_UART_SIZE - 1) & 0xfff00000)
+
+/* Board-specific IRQ info */
+#define	EV64260_UART_0_IRQ		85
+#define	EV64260_UART_1_IRQ		86
+#define	EV64260_PCI_0_IRQ		91
+#define	EV64260_PCI_1_IRQ		93
+
+/* Serial port setup */
+#define	EV64260_DEFAULT_BAUD		115200
+
+#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
+#define SERIAL_PORT_DFNS
 
-#define	EV64260_TODC_BASE		0xfc800000
-#define	EV64260_TODC_LEN		0x00800000
-#define	EV64260_TODC_END		(EV64260_TODC_BASE + \
-					 EV64260_TODC_LEN - 1)
-
-#define	EV64260_UART_BASE		0xfd000000
-#define	EV64260_UART_LEN		0x00800000
-#define	EV64260_UART_END		(EV64260_UART_BASE + \
-					 EV64260_UART_LEN - 1)
-/* Serial driver setup.  */
+#define	EV64260_MPSC_CLK_SRC		8		/* TCLK */
+#define	EV64260_MPSC_CLK_FREQ		100000000	/* 100MHz clk */
+#else
 #define EV64260_SERIAL_0		(EV64260_UART_BASE + 0x20)
 #define EV64260_SERIAL_1		EV64260_UART_BASE
 
-#define BASE_BAUD ( 3686400 / 16 )
+#define BASE_BAUD	(EV64260_DEFAULT_BAUD * 2)
 
 #ifdef CONFIG_SERIAL_MANY_PORTS
 #define RS_TABLE_SIZE	64
@@ -50,18 +115,14 @@
 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
 #endif
 
-#if	!defined(CONFIG_GT64260_CONSOLE)
 /* Required for bootloader's ns16550.c code */
 #define STD_SERIAL_PORT_DFNS 						\
-        { 0, BASE_BAUD, EV64260_SERIAL_0, 85, STD_COM_FLAGS, /* ttyS0 */\
-	iomem_base: (u8 *)EV64260_SERIAL_0,				\
+        { 0, BASE_BAUD, EV64260_SERIAL_0, EV64260_UART_0_IRQ, STD_COM_FLAGS, \
+	iomem_base: (u8 *)EV64260_SERIAL_0,	/* ttyS0 */		\
 	iomem_reg_shift: 2,						\
 	io_type: SERIAL_IO_MEM },
 
 #define SERIAL_PORT_DFNS \
         STD_SERIAL_PORT_DFNS
-#else
-#define SERIAL_PORT_DFNS
 #endif
-
 #endif /* __PPC_PLATFORMS_EV64260_H */
diff -L arch/ppc/platforms/ev64260_setup.c -puN arch/ppc/platforms/ev64260_setup.c~ppc32-support-for-marvell-ev-64260-bp-eval-platform /dev/null
--- 25/arch/ppc/platforms/ev64260_setup.c
+++ /dev/null	Thu Apr 11 07:25:15 2002
@@ -1,476 +0,0 @@
-/*
- * arch/ppc/platforms/ev64260_setup.c
- *
- * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * The EV-64260-BP port is the result of hard work from many people from
- * many companies.  In particular, employees of Marvell/Galileo, Mission
- * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
- */
-#include <linux/config.h>
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/ide.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#if	!defined(CONFIG_GT64260_CONSOLE)
-#include <linux/serial.h>
-#endif
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/smp.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/gt64260.h>
-#include <platforms/ev64260.h>
-
-
-extern char cmd_line[];
-unsigned long ev64260_find_end_of_memory(void);
-
-TODC_ALLOC();
-
-/*
- * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
- */
-static int __init
-ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	struct pci_controller	*hose = pci_bus_to_hose(dev->bus->number);
-
-	if (hose->index == 0) {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 * 	   A   B   C   D
-		 */
-		{
-			{ 91, 0, 0, 0 },	/* IDSEL 7 - PCI bus 0 */
-			{ 91, 0, 0, 0 },	/* IDSEL 8 - PCI bus 0 */
-		};
-
-		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	}
-	else {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 * 	   A   B   C   D
-		 */
-		{
-			{ 93, 0, 0, 0 },	/* IDSEL 7 - PCI bus 1 */
-			{ 93, 0, 0, 0 },	/* IDSEL 8 - PCI bus 1 */
-		};
-
-		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	}
-}
-
-static void __init
-ev64260_setup_bridge(void)
-{
-	gt64260_bridge_info_t		info;
-	int				window;
-
-	GT64260_BRIDGE_INFO_DEFAULT(&info, ev64260_find_end_of_memory());
-
-	/* Lookup PCI host bridges */
-	if (gt64260_find_bridges(EV64260_BRIDGE_REG_BASE,
-				 &info,
-				 ev64260_map_irq)) {
-		printk("Bridge initialization failed.\n");
-	}
-
-	/*
-	 * Enabling of PCI internal-vs-external arbitration
-	 * is a platform- and errata-dependent decision.
-	 */
-	if(gt64260_revision == GT64260)  {
-		/* FEr#35 */
-		gt_clr_bits(GT64260_PCI_0_ARBITER_CNTL, (1<<31));
-		gt_clr_bits(GT64260_PCI_1_ARBITER_CNTL, (1<<31));
-	} else if( gt64260_revision == GT64260A )  {
-		gt_set_bits(GT64260_PCI_0_ARBITER_CNTL, (1<<31));
-		gt_set_bits(GT64260_PCI_1_ARBITER_CNTL, (1<<31));
-		/* Make external GPP interrupts level sensitive */
-		gt_set_bits(GT64260_COMM_ARBITER_CNTL, (1<<10));
-		/* Doc Change 9: > 100 MHz so must be set */
-		gt_set_bits(GT64260_CPU_CONFIG, (1<<23));
-	}
-
-	gt_set_bits(GT64260_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
-
-	/* SCS windows not disabled above, disable all but SCS 0 */
-	for (window=1; window<GT64260_CPU_SCS_DECODE_WINDOWS; window++) {
-		gt64260_cpu_scs_set_window(window, 0, 0);
-	}
-
-	/* Set up windows to RTC/TODC and DUART on device module (CS 1 & 2) */
-	gt64260_cpu_cs_set_window(1, EV64260_TODC_BASE, EV64260_TODC_LEN);
-	gt64260_cpu_cs_set_window(2, EV64260_UART_BASE, EV64260_UART_LEN);
-
-	/*
-	 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
-	 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
-	 * register).  Need to route the MPP inputs to the GPP and set the
-	 * polarity correctly.
-	 *
-	 * In MPP Control 2 Register
-	 *   MPP 21 -> GPP 21 (DUART channel A intr)
-	 *   MPP 22 -> GPP 22 (DUART channel B intr)
-	 *
-	 * In MPP Control 3 Register
-	 *   MPP 27 -> GPP 27 (PCI 0 INTA)
-	 *   MPP 29 -> GPP 29 (PCI 1 INTA)
-	 */
-	gt_clr_bits(GT64260_MPP_CNTL_2,
-			       ((1<<20) | (1<<21) | (1<<22) | (1<<23) |
-			        (1<<24) | (1<<25) | (1<<26) | (1<<27)));
-
-	gt_clr_bits(GT64260_MPP_CNTL_3,
-			       ((1<<12) | (1<<13) | (1<<14) | (1<<15) |
-			        (1<<20) | (1<<21) | (1<<22) | (1<<23)));
-
-	gt_write(GT64260_GPP_LEVEL_CNTL, 0x000002c6);
-
-	/* DUART & PCI interrupts are active low */
-	gt_set_bits(GT64260_GPP_LEVEL_CNTL,
-			     ((1<<21) | (1<<22) | (1<<27) | (1<<29)));
-
-	/* Clear any pending interrupts for these inputs and enable them. */
-	gt_write(GT64260_GPP_INTR_CAUSE,
-			  ~((1<<21) | (1<<22) | (1<<27) | (1<<29)));
-	gt_set_bits(GT64260_GPP_INTR_MASK,
-			     ((1<<21) | (1<<22)| (1<<27) | (1<<29)));
-	gt_set_bits(GT64260_IC_CPU_INTR_MASK_HI, ((1<<26) | (1<<27)));
-
-	/* Set MPSC Multiplex RMII */
-	/* NOTE: ethernet driver modifies bit 0 and 1 */
-	gt_write(GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
-
-	return;
-}
-
-
-static void __init
-ev64260_setup_arch(void)
-{
-#if	!defined(CONFIG_GT64260_CONSOLE)
-	struct serial_struct	serial_req;
-#endif
-
-	if ( ppc_md.progress )
-		ppc_md.progress("ev64260_setup_arch: enter", 0);
-
-	loops_per_jiffy = 50000000 / HZ;
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef	CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	if ( ppc_md.progress )
-		ppc_md.progress("ev64260_setup_arch: find_bridges", 0);
-
-	/*
-	 * Set up the L2CR register.
-	 * L2 cache was invalidated by bootloader.
-	 */
-	switch (PVR_VER(mfspr(PVR))) {
-		case PVR_VER(PVR_750):
-			_set_L2CR(0xfd100000);
-			break;
-		case PVR_VER(PVR_7400):
-		case PVR_VER(PVR_7410):
-			_set_L2CR(0xcd100000);
-			break;
-		/* case PVR_VER(PVR_7450): */
-			/* XXXX WHAT VALUE?? FIXME */
-			break;
-	}
-
-	ev64260_setup_bridge();
-
-	TODC_INIT(TODC_TYPE_DS1501, 0, 0, ioremap(EV64260_TODC_BASE,0x20), 8);
-
-#if	!defined(CONFIG_GT64260_CONSOLE)
-	memset(&serial_req, 0, sizeof(serial_req));
-	serial_req.line = 0;
-	serial_req.baud_base = BASE_BAUD;
-	serial_req.port = 0;
-	serial_req.irq = 85;
-	serial_req.flags = STD_COM_FLAGS;
-	serial_req.io_type = SERIAL_IO_MEM;
-	serial_req.iomem_base = ioremap(EV64260_SERIAL_0, 0x20);
-	serial_req.iomem_reg_shift = 2;
-
-	if (early_serial_setup(&serial_req) != 0) {
-		printk("Early serial init of port 0 failed\n");
-	}
-
-	/* Assume early_serial_setup() doesn't modify serial_req */
-	serial_req.line = 1;
-	serial_req.port = 1;
-	serial_req.irq = 86;
-	serial_req.iomem_base = ioremap(EV64260_SERIAL_1, 0x20);
-
-	if (early_serial_setup(&serial_req) != 0) {
-		printk("Early serial init of port 1 failed\n");
-	}
-#endif
-
-	printk("Marvell/Galileo EV-64260-BP Evaluation Board\n");
-	printk("EV-64260-BP port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
-
-	if ( ppc_md.progress )
-		ppc_md.progress("ev64260_setup_arch: exit", 0);
-
-	return;
-}
-
-static void __init
-ev64260_init_irq(void)
-{
-	gt64260_init_irq();
-
-	if(gt64260_revision != GT64260)  {
-		/* XXXX Kludge--need to fix gt64260_init_irq() interface */
-		/* Mark PCI intrs level sensitive */
-		irq_desc[91].status |= IRQ_LEVEL;
-		irq_desc[93].status |= IRQ_LEVEL;
-	}
-}
-
-unsigned long __init
-ev64260_find_end_of_memory(void)
-{
-	return 32*1024*1024;	/* XXXX FIXME */
-}
-
-static void
-ev64260_reset_board(void)
-{
-	local_irq_disable();
-
-	/* Set exception prefix high - to the firmware */
-	_nmask_and_or_msr(0, MSR_IP);
-
-	/* XXX FIXME */
-	printk("XXXX **** trying to reset board ****\n");
-	return;
-}
-
-static void
-ev64260_restart(char *cmd)
-{
-	volatile ulong	i = 10000000;
-
-	ev64260_reset_board();
-
-	while (i-- > 0);
-	panic("restart failed\n");
-}
-
-static void
-ev64260_halt(void)
-{
-	local_irq_disable();
-	while (1);
-	/* NOTREACHED */
-}
-
-static void
-ev64260_power_off(void)
-{
-	ev64260_halt();
-	/* NOTREACHED */
-}
-
-static int
-ev64260_show_cpuinfo(struct seq_file *m)
-{
-	uint pvid;
-
-	pvid = mfspr(PVR);
-	seq_printf(m, "vendor\t\t: Marvell/Galileo\n");
-	seq_printf(m, "machine\t\t: EV-64260-BP\n");
-	seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
-			pvid, (pvid & (1<<15) ? "IBM" : "Motorola"));
-
-	return 0;
-}
-
-/* DS1501 RTC has too much variation to use RTC for calibration */
-static void __init
-ev64260_calibrate_decr(void)
-{
-	ulong freq;
-
-	freq = 100000000 / 4;
-
-	printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
-	       freq/1000000, freq%1000000);
-
-	tb_ticks_per_jiffy = freq / HZ;
-	tb_to_us = mulhwu_scale_factor(freq, 1000000);
-
-	return;
-}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG)
-/*
- * Set BAT 3 to map 0xf0000000 to end of physical memory space.
- */
-static __inline__ void
-ev64260_set_bat(void)
-{
-	unsigned long   bat3u, bat3l;
-	static int	mapping_set = 0;
-
-	if (!mapping_set) {
-
-		__asm__ __volatile__(
-		" lis %0,0xf000\n \
-		  ori %1,%0,0x002a\n \
-		  ori %0,%0,0x1ffe\n \
-		  mtspr 0x21e,%0\n \
-		  mtspr 0x21f,%1\n \
-		  isync\n \
-		  sync "
-		: "=r" (bat3u), "=r" (bat3l));
-
-		mapping_set = 1;
-	}
-
-	return;
-}
-
-#if !defined(CONFIG_GT64260_CONSOLE)
-#include <linux/serialP.h>
-#include <linux/serial_reg.h>
-#include <asm/serial.h>
-
-static struct serial_state rs_table[RS_TABLE_SIZE] = {
-	SERIAL_PORT_DFNS	/* Defined in <asm/serial.h> */
-};
-
-static void
-ev64260_16550_progress(char *s, unsigned short hex)
-{
-	volatile char c;
-	volatile unsigned long com_port;
-	u16 shift;
-
-	com_port = rs_table[0].port;
-	shift = rs_table[0].iomem_reg_shift;
-
-	while ((c = *s++) != 0) {
-		while ((*((volatile unsigned char *)com_port +
-				(UART_LSR << shift)) & UART_LSR_THRE) == 0)
-		                ;
-	        *(volatile unsigned char *)com_port = c;
-
-		if (c == '\n') {
-			while ((*((volatile unsigned char *)com_port +
-				(UART_LSR << shift)) & UART_LSR_THRE) == 0)
-					;
-	        	*(volatile unsigned char *)com_port = '\r';
-		}
-	}
-
-	/* Move to next line on */
-	while ((*((volatile unsigned char *)com_port +
-		(UART_LSR << shift)) & UART_LSR_THRE) == 0)
-			;
-	*(volatile unsigned char *)com_port = '\n';
-	while ((*((volatile unsigned char *)com_port +
-		(UART_LSR << shift)) & UART_LSR_THRE) == 0)
-			;
-	*(volatile unsigned char *)com_port = '\r';
-
-	return;
-}
-#endif	/* !CONFIG_GT64260_CONSOLE */
-#endif	/* CONFIG_SERIAL_TEXT_DEBUG */
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-	isa_mem_base = 0;
-
-	ppc_md.setup_arch = ev64260_setup_arch;
-	ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
-	ppc_md.irq_canonicalize = NULL;
-	ppc_md.init_IRQ = ev64260_init_irq;
-	ppc_md.get_irq = gt64260_get_irq;
-	ppc_md.init = NULL;
-
-	ppc_md.restart = ev64260_restart;
-	ppc_md.power_off = ev64260_power_off;
-	ppc_md.halt = ev64260_halt;
-
-	ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
-
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.calibrate_decr = ev64260_calibrate_decr;
-
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-
-	ppc_md.heartbeat = NULL;
-	ppc_md.heartbeat_reset = 0;
-	ppc_md.heartbeat_count = 0;
-
-#ifdef	CONFIG_SERIAL_TEXT_DEBUG
-	ev64260_set_bat();
-#ifdef	CONFIG_GT64260_CONSOLE
-	gt64260_base = EV64260_BRIDGE_REG_BASE;
-	ppc_md.progress = gt64260_mpsc_progress; /* embedded UART */
-#else
-	ppc_md.progress = ev64260_16550_progress; /* Dev module DUART */
-#endif
-#else	/* !CONFIG_SERIAL_TEXT_DEBUG */
-	ppc_md.progress = NULL;
-#endif	/* CONFIG_SERIAL_TEXT_DEBUG */
-
-	return;
-}
diff -puN arch/ppc/platforms/Makefile~ppc32-support-for-marvell-ev-64260-bp-eval-platform arch/ppc/platforms/Makefile
--- 25/arch/ppc/platforms/Makefile~ppc32-support-for-marvell-ev-64260-bp-eval-platform	Fri Nov 19 16:00:10 2004
+++ 25-akpm/arch/ppc/platforms/Makefile	Fri Nov 19 16:00:10 2004
@@ -23,7 +23,7 @@ obj-$(CONFIG_PREP_RESIDUAL)	+= residual.
 obj-$(CONFIG_ADIR)		+= adir_setup.o adir_pic.o adir_pci.o
 obj-$(CONFIG_PQ2ADS)		+= pq2ads.o
 obj-$(CONFIG_TQM8260)		+= tqm8260_setup.o
-obj-$(CONFIG_EV64260)		+= ev64260_setup.o
+obj-$(CONFIG_EV64260)		+= ev64260.o
 obj-$(CONFIG_GEMINI)		+= gemini_pci.o gemini_setup.o gemini_prom.o
 obj-$(CONFIG_K2)		+= k2.o
 obj-$(CONFIG_LOPEC)		+= lopec.o
diff -puN arch/ppc/syslib/Makefile~ppc32-support-for-marvell-ev-64260-bp-eval-platform arch/ppc/syslib/Makefile
--- 25/arch/ppc/syslib/Makefile~ppc32-support-for-marvell-ev-64260-bp-eval-platform	Fri Nov 19 16:00:10 2004
+++ 25-akpm/arch/ppc/syslib/Makefile	Fri Nov 19 16:00:10 2004
@@ -40,8 +40,7 @@ obj-$(CONFIG_PPC_PREP)		+= open_pic.o in
 obj-$(CONFIG_ADIR)		+= i8259.o indirect_pci.o pci_auto.o \
 					todc_time.o
 obj-$(CONFIG_EBONY)		+= indirect_pci.o pci_auto.o todc_time.o
-obj-$(CONFIG_EV64260)		+= gt64260_common.o gt64260_pic.o \
-					indirect_pci.o todc_time.o pci_auto.o
+obj-$(CONFIG_EV64260)		+= todc_time.o pci_auto.o
 obj-$(CONFIG_GEMINI)		+= open_pic.o indirect_pci.o
 obj-$(CONFIG_GT64260)		+= gt64260_pic.o
 obj-$(CONFIG_K2)		+= i8259.o indirect_pci.o todc_time.o \
_
